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Hi everyone!
I'm trying to connect the two ethernet ports on DE2-115. Basically, I just want to bypass the signal between the two ports without any code/decode protocol. I'am trying to perform this task just in the PHY/MAC layers. I already tryied some codes, but i didn't manage it. Could anyone help me on this?
One of my used codes is:
module com_eth0_eth1(
clock_50,
enet0_tx_data,
enet0_gtx_clk,
enet0_tx_clk,
enet0_tx_en,
enet0_tx_er,
enet0_rx_data,
enet0_rx_clk,
enet0_rx_dv,
enet0_rx_er,
enet1_tx_data,
enet1_gtx_clk,
enet1_tx_clk,
enet1_tx_en,
enet1_tx_er,
enet1_rx_data,
enet1_rx_clk,
enet1_rx_dv,
enet1_rx_er
);
// Ethernet0
output enet0_gtx_clk, enet0_tx_clk;
input enet0_rx_clk;
// Ethernet1
output enet1_gtx_clk, enet1_tx_clk;
input enet1_rx_clk;
// Saídas
// Ethernet 0
output [3:0] enet0_tx_data;
output enet0_tx_en, enet0_tx_er;
// Ethernet 1
output [3:0] enet1_tx_data;
output enet1_tx_en, enet1_tx_er;
// Entradas
// Ethernet 0
input [3:0] enet0_rx_data;
input enet0_rx_dv, enet0_rx_er;
// Ethernet 1
input [3:0] enet1_rx_data;
input enet1_rx_dv, enet1_rx_er;
reg [3:0] enet0_tx_data;
reg enet0_tx_en, enet0_tx_er;
reg [3:0] enet1_tx_data;
reg enet1_tx_en, enet1_tx_er;
reg enet0_gtx_clk, enet1_gtx_clk, enet0_tx_clk, enet1_tx_clk;
reg ledr0, ledr1, ledg0, ledg1;
// Funcionamento do circuito
always @(posedge enet0_rx_clk or posedge enet1_rx_clk)
begin
enet0_gtx_clk <= enet1_rx_clk;
enet1_gtx_clk <= enet0_rx_clk;
enet0_tx_clk <= enet1_rx_clk;
enet1_tx_clk <= enet0_rx_clk;
enet1_tx_en <= enet0_rx_dv;
enet1_tx_data <= enet0_rx_data;
enet1_tx_er <= enet0_rx_er;
enet0_tx_en <= enet1_rx_dv;
enet0_tx_data <= enet1_rx_data;
enet0_tx_er <= enet1_rx_er;
end
endmodule
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Hi,
DE2 is an old device. And when I looked up for it, It has only one ethernet port. So, are you using two boards and trying to bypass the MAC layers between both of the boards? And based on DE2 layout, it does has External Ethernet PHY. You may can simply send signal without compliance or using protocol that match with external PHY.
Do let me know it it helps.
Regards,
Pavee
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I really appreciate your attention on my question! Thx a lot!
So... the DE2-115 board does have two ethernet transciever with two conectors RJ45 in a single board.
My goal is to send and receive data from one port to other without using any protocol, just perform a MAC to MAC connection using RGMII. I tried using the code I posted before but with it I'm just receiving data but not transmiting... I think is a problem with clock or with the TX_enable pins... but I still didn't get it to work.
Do you have any clues?
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Correct the DE2-115 is an old board, but it does have two complete etherNet PHY transceivers and RJ45 connectors, ETH0 and ETH1.
You are definitely going to want to get the full 88E1111 datasheet ...
... which will allow you to configure and program the device registers.
TerAsic only distributes the shorter 88E1111 product brief which only has the external electrical/pin connections, no register info.
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Thanks a lot about yout attention!!
Yes! the board is a little old indeed... but it have the two ethernet ports as you said.
I alrealdy read the datasheet available but it is not really clear about how to perform those configurations. But still I think is no necessary do any changes on it... When I lunch the code into the board I can see I'am receiving data but I am not sending ... I think maybe is a problem with the TX clock or TX enable pins... any clues?
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How do you configure the 88E1111 devices? You show no code for that.
I don't believe they will be enabled to transmit without configuration register setup.
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I didn't configured it... I just assigned the pins TX-->RX from one port to the other.
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Are you, or are are you not, passing that data thru the two external 88E1111 PHY/MAC devices?
I assumed this is what you are trying to do.
Or are you just trying to connect the two etherNet MAC modules together INSIDE the FPGA device?
I can't tell which from the code you posted, since you don't indicate which signals, if any, are pins on the FPGA, or just internal nodes.
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I am trying to connect inside the FPGA...
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Hi,
I believe to transmit the data between 2 port it requires registers configuration setup first but unfortunately the datasheet doesn't provide any information on registers. And Intel does not have any document regarding this device.
Regards,
Pavee
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I managed to get it... it was just a clock issue... no need at all to configure setup.
I thank al attention!!
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We do not receive any response from you to the previous question that I have provided and I believe register configuration is mandatory for transmitting the data. This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.

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