I watched this movie before. From this video I learned that ADC can be simulated.
This video shows how to add an extended output file to the ADC simulation. But my problem is that the simulation does not generate ADC and PLL output signals.
Probably I have a error somewhere. I am a beginner, and I can not find my mistake.
You have to include the test bench in Quartus project you need to change the settings to include your testbench.
Settings->EDA Tools Setting ->simulation -> select compile testbench ->click testbenches->click new and add the file generated ->ok->apply->ok
Add .vht file in quartus and start analysis and elaboration and launch Modelsim.
Refer below link for steps
thank you for the support.
Below I will explain my mistakes
And I show what I corrected that the simulation started correctly.
remove *.sip file from project
1 Option change to Verilog HDL 1 ps
2 Add testbench. TestBench name is important. Must be The same as top level entity
on this video I show step by step how to do it correctly https://youtu.be/YbOnfNFJg6Y