Simulate ADC PLL FPGA MAX10

[mmare6]

On this video I try simulate PLL https://youtu.be/Yf15rAGqxQw

My target is to simulate the ADC module. But at the moment simulation of the PLL module does not work. what am I doing wrong ??

[AnandRaj_S_Intel]

​Hi,

To perform the ADC simulation in Max® 10 device please check below link.

https://www.youtube.com/watch?v=6UscboZ1Vho

Regards

Anand

[mmare6]

I watched this movie before. From this video I learned that ADC can be simulated.

This video shows how to add an extended output file to the ADC simulation. But my problem is that the simulation does not generate ADC and PLL output signals.

Probably I have a error somewhere. I am a beginner, and I can not find my mistake.

[AnandRaj_S_Intel]

​Hi,

You have to include the test bench in Quartus project you need to change the settings to include your testbench.

Settings->EDA Tools Setting ->simulation -> select compile testbench ->click testbenches->click new and add the file generated ->ok->apply->ok

Add .vht file in quartus and start analysis and elaboration and launch Modelsim.

Refer below link for steps

http://denethor.wlu.ca/pc120/quartus_testbench.shtml

Regards

Anand

[mmare6]

thank you for the support.

Below I will explain my mistakes

And I show what I corrected that the simulation started correctly.

remove *.sip file from project

1 Option change to Verilog HDL 1 ps

2 Add testbench. TestBench name is important. Must be The same as top level entity

on this video I show step by step how to do it correctly https://youtu.be/YbOnfNFJg6Y