Hi, I am working with a MAX10 and have instantiated the Soft LVDS core. I would like to use ModelSIM (the starter edition set up with NativeLink directly from Quartus) to simulate the behavior. However, when I open modelsim with my compiled design I get:
** Error: (vsim-3033) (private_path)/transmitter.v(56): Instantiation of 'fiftyfivenm_ddio_out' failed. The design unit was not found.
plus 9 other error's similar. I have attempted the simple counter (LPM counter) IP as well, and I get a similar error, indicating the LPM Counter design unit was not found. Is there a setting I am missing to simulate the Altera IP Cores? (I had the same error using 18.1)
Thanks for your help!
Have you instantiated the 'Soft LVDS core'module in main design?
Before compilation of project, create hdl file/inst. file for used IP & instantiate in main design.
(This message was posted on behalf of Intel Corporation)
I have insantiated the module in my top level design. From the errors in modelsim and when I have tried other Altera IP (which also do not work, such as the LPM counter) I get an error in modelsim that seems to indicate that ModelSIM can't find the path to the verilog underlying module, such as the LPM_counter. Even though I believe my nativelonk is set up correctly.