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Simulating Altera IP Cores in Quartus Prime Lite 16.1 (or beyond)

TMayd
Novice
1,600 Views

Hi, I am working with a MAX10 and have instantiated the Soft LVDS core. I would like to use ModelSIM (the starter edition set up with NativeLink directly from Quartus) to simulate the behavior. However, when I open modelsim with my compiled design I get:

 

** Error: (vsim-3033) (private_path)/transmitter.v(56): Instantiation of 'fiftyfivenm_ddio_out' failed. The design unit was not found.

 

plus 9 other error's similar. I have attempted the simple counter (LPM counter) IP as well, and I get a similar error, indicating the LPM Counter design unit was not found. Is there a setting I am missing to simulate the Altera IP Cores? (I had the same error using 18.1)

 

Thanks for your help!

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4 Replies
Vicky1
Employee
251 Views

Hi,

Have you instantiated the 'Soft LVDS core'module in main design?

Before compilation of project, create hdl file/inst. file for used IP & instantiate in main design.

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

 

TMayd
Novice
251 Views

Hi Vikas,

I​ have insantiated the module in my top level design. From the errors in modelsim and when I have tried other Altera IP (which also do not work, such as the LPM counter) I get an error in modelsim that seems to indicate that ModelSIM can't find the path to the verilog underlying module, such as the LPM_counter. Even though I believe my nativelonk is set up correctly.

Tyler​

Vicky1
Employee
251 Views

Hi Tyler,

Can you share your project file?

 

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

TMayd
Novice
251 Views
Hi Vikas, I realized Nativelink did not automatically compile the libraries necessary for simulation. So instantiating in VHDL makes this problem go away, however I still had to go and manually compile the libraries into my workspace. So it's working now, just not as seamless as I thought. Tyler
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