Simulating NIOS2 with Custom Testbench in Modelsim

Altera_Forum · ‎09-10-2014

Hi,

I am trying to simulate a very simple NIOS2 design using a custom testbench. The NIOS2 simply sets a PIO pin, but I am not able to see this in the simulation waveforms.

First off, I have followed the (quite helpful) simulation tutorial from (http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_mm_tutorial.pdf), but I'm still having trouble. It's probably something very simple, but I can't figure out what the issue is. Details are below:

qsys system

A picture is attached. But basically it includes:
A NIOS2 standard processor with cache and level 1 debugging.
An on-chip 20KB memory for NIOS data/instructions
The memory is initialized to the .hex file that was built by Eclipse SBT and stored in the synthesis folder (I have tried both automatic initialization, and custom by pointing directly to the .hex file)
Two 1-bit PIO output ports that reset to 0.
Simulation and synthesis files are generated.

eclipse application

The nios2 code is below.

# include "system.h"# include "altera_avalon_pio_regs.h"
int main(){
    while(1){
        IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0);
        IOWR_ALTERA_AVALON_PIO_DATA(PIO_1_BASE, 1);
    }
}

verilog top-level module and testbench

Top-level module:


//top-level module
module desperation(
    input clk,
    input reset,
    output out,
    output out2
);
    nios_test u0 (
        .clk_clk (clk),       
        .reset_reset_n (reset),
        .out_export (out),    
        .out2_export (out2)
    );
     
endmodule

Testbench:


//testbench
`timescale 1 ns / 1 ps
module desperation_tb();
reg clk;
wire reset;
wire out;
wire out2;
//50MHz
initial clk = 1'b0;
always# 10 clk = ~clk;
//have tried both reset low and reset high
assign reset = 1'b1;
desperation dut
(
    .clk(clk),
    .reset(reset),
    .out(out),
    .out2(out2)
);
endmodule

modelsim simulation script

.main clear
set BASE_DIR <some_dir>
set TOP_LEVEL_NAME desperation
set TESTBENCH_NAME desperation_tb
set QSYS_PROJ_NAME nios_test
cd $BASE_DIR/$QSYS_PROJ_NAME/simulation/mentor
source msim_setup.tcl
dev_com
com
vlog -sv ../../../$TOP_LEVEL_NAME.v
vlog -sv ../../../$TESTBENCH_NAME.v
set TOP_LEVEL_NAME $TESTBENCH_NAME
elab +nowarnTFMPC
add wave -position end  sim:/$TESTBENCH_NAME/dut/clk
add wave -position end  sim:/$TESTBENCH_NAME/dut/reset
add wave -position end  sim:/$TESTBENCH_NAME/dut/out
add wave -position end  sim:/$TESTBENCH_NAME/dut/out2
run 10us

It's worth noting that the result is the same from this modelsim script and when I try to run gate-level simulation through NativeLink in Quartus. Basically both NIOS2 outputs stay low, while according to the NIOS2 code one should go high while the other remains low.

I'm very new to both Qsys and NIOS2, so I don't know if I'm doing something wrong (incorrectly generating Qsys system / Eclipse build; not properly instantiating NIOS2 memory for simulation, etc). I have followed both the introductory NIOS2 software and hardware tutorials for setting up Qsys and Eclipse, but I'm still having trouble.

Any tips would be great!