Hello everyone,
I am a new user of Quartus, and I have had the experience of using Quartus to make some simple projects in the past few weeks. Recently I updated my computer to windows 11 and reinstalled and upgraded Quartus to version 22.1std, but after this I found that the files that used to run successfully now have the same problem, the problem is as follows :
When I want to create a waveform file with a .v file (used with Quartus Prime 22.1std). The following error code appears after using Simulation Waveform Editor.
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/22.1std/questa_fe/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off addsub_4 -c addsub_4 --vector_source="C:/Users/CTong/Desktop/addsub_4/add_4.vwf" --testbench_file="C:/Users/CTong/Desktop/addsub_4/simulation/qsim/add_4.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Wed May 3 16:06:43 2023
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off addsub_4 -c addsub_4 --vector_source=C:/Users/CTong/Desktop/addsub_4/add_4.vwf --testbench_file=C:/Users/CTong/Desktop/addsub_4/simulation/qsim/add_4.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/CTong/Desktop/addsub_4/simulation/qsim/" addsub_4 -c addsub_4
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Wed May 3 16:06:44 2023
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/Users/CTong/Desktop/addsub_4/simulation/qsim/ addsub_4 -c addsub_4
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file addsub_4.vo in folder "C:/Users/CTong/Desktop/addsub_4/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4648 megabytes
Info: Processing ended: Wed May 3 16:06:44 2023
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00
Completed successfully.
**** Generating the ModelSim .do script ****
C:/Users/CTong/Desktop/addsub_4/simulation/qsim/addsub_4.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/22.1std/questa_fe/win64//vsim -c -do addsub_4.do
Error.
Through this error code, I can't point out what specific problems occurred, but here is what I tried to do.
1. romove -novopt in "simulation options" in the Simulation Waveform Editor
2. "simulation options" in the Simulation Waveform Editor and change vsim -novopt to vsim -voptargs="+acc".
3. make sure I have a specific EDA tool in my settings(All the tools have been tried but have the same error code,so I guess it's not the tool's problem)
Am I missing something?
Thank you all very much in advance!
Greetings from Taiwan,
Tong
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