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MCost7
Beginner
1,208 Views

Simulation behavior didn't match with synthesized design

The quartus version 18.1 is used, the target FPGA is Stratix IV.

The code that is not correctly synthesized is:

     assign  addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000);

But the simulation behavior is the same of the synthesized design if I use instead:

      wire dst_0 = ~dst[2] & ~dst[1] & ~dst[0];

     wire dst_1 = ~dst[2] & ~dst[1] & dst[0];

      assign addr = (sel1 & sel2) ? dst_1 : dst_0;

 

Are something used on the first approach that is not supported by quartus?

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3 Replies
Vicky1
Employee
38 Views

Hi,

In First approach   'assign addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000);'

dst covers only two combinations : 3'b001 & 3'b000.

In Second approach dst covers multiple combinations : 3'b000 ,3'b111,3'b001 ,3'b011 etc.

So it`s obvious that variation in Quartus report.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

Pvand1
Novice
38 Views

I'm not really familiarwith Verilog, but it seems to me the second part is only equal to the first part when dst = 3'b000

Does your simulion cover all the cases?

Do you have timing issues?

I might have missed deleted comments but I don't see anything about a quartus report that the above posts mentions.

Vicky1
Employee
38 Views

Hi,

  • 'I'm not really familiar with Verilog, but it seems to me the second part is only equal to the first part when dst = 3'b000'

Yes, you are correct, first part covers only two combination out of all combination( as in 2nd part).

Please go through the Online training,

https://www.intel.com/content/www/us/en/programmable/support/training/course/ohdl1120.html

  • 'Does your simulion cover all the cases?'

It should be.

  • 'I might have missed deleted comments but I don't see anything about a quartus report that the above posts mentions.'

Quartus report here I mean Quartus synthesis & simulation results.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar 

(This message was posted on behalf of Intel Corporation)

 

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