Greetings all, I have designed a simple multiplexing system in Quartus II. Now, I have downloaded the project into a DE2 board and would like to see the result but I don't want the result to be the LEDs. I want so see the waveforms. My question is which one to use: Quartus Simulator or Modelsim??? And is Simulation considered the same as displaying??? Because I want to see exactly what I did, but I think simulation is controlled by the user. Thanks
Simulation takes your code and simulates its. Modelsim is a much more powerful simulator capable of more control, and will simulate much faster as it simulates your code directly. Quartus simulator simulates the compiled design at the gate level, and is much slower, and also much less powerfulIf you set it up right, you will see everyting in the design.
Thank you very much indeed. But now I have another problem. I have designed my project in Block Diagram/Schematics. Now I want to simulate this in ModelSim. Do I have to convert every block into VHDL? If so, which VHDL file do I have to compile??? Do you take only the top_level design or every design file??? I really need help in this matter. Thanks.
Some clarification to the above. First of all, there is no such thing as "Quartus Simulation". Quartus hasn't included a simulation tool for a long time. You use the ModelSim-Altera simulation tool included with your installation of Quartus (or your own simulation tool if you have a license). You can perform RTL simulation, which simulates just the functionality of your design, or a gate-level simulation, which tests functionality but also factors in gate delays through your target device. In most cases, you'll just use RTL simulation along with TimeQuest timing analysis to verify your design. Performing a gate-level simulation is more complicated to set up and takes longer to run. Second, you should be able to convert your entire schematic into an HDL (Verilog or VHDL) right from the schematic editor from the top-level. I haven't done this in a long time, so maybe you do have to manually choose to convert each and every block in your schematic. Any IP will not require a conversion because IP is already generated as HDL in the background when you add it to your design.Steve
Just to clarify a bit more. You can not only convert your top level schematic into VHDL or Verilog from the schematic editor, you can have it done automatically each time you re-compile. This saves time. Also, Quartus DOES have a simulator built-in (it actually runs ModelSim for you) which, for simple designs, I believe is easier to use than ModelSim. Start by creating a new "vector waveform file" for your simulation (File-> New -> Verification/Debug Files -> University Program VWF). You should search Google and YouTube for instructions on how to go from there.