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Altera_Forum
Honored Contributor I
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Simulink “FPGA in the Loop” with QSYS-Components

In Simulink you can use the “FPGA-in-the-Loop” wizard to generate blocks, which run during the simulation time on the FPGA hardware. Basically, you create a Quartus project and feed all generated HDL files in this wizard and he generates a Ready to Use Simulink block.  

 

I own a “ Terasic DE2-115” board and went through the tutorials and examples of my Matlab(R2017a) installation relating to this topic and I’ve also created some own examples with “Quartus Prime 17” and Megafunctions like “lpm_add_sub” etc. Everything works fine! 

 

However, when I do the same steps and use QSYS-components in the Quartus project I get errors during the compilation. The Wizard calls Quartus and Quartus always reports for example:  

 

node instance "merlin_master_translator" instantiates undefined entity "altera_merlin_master_translator". ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. if this entity represents intel fpga or third-party ip, generate the synthesis files for the ip. 

 

It seems Quartus can’t find necessary libraries for the involved QSYS IP components. If I compile the same project direct in Quartus I get no errors (..except the infos about the unused inputs/outputs for Simulink)! Unfortunately, there is apparently no way to generate the desired block then. 

 

I’ve attached a very simple example (see: QSYS_FIL.zip) 

Let’s say I want to replace the “DE2-115 Flash” block with a Hardware(FIL) block and read the first 16 values of the onboard flash. (see: 1_Simulink.PNG)https://www.alteraforum.com/forum/attachment.php?attachmentid=14092&stc=1

First, I create a flash controller with QSYS using three IP cores: clock, flash ip and Avalon MM Master Translator and afterwards I connect the pins with the FPGA. 

 

Now I enter all generated files in the wizard, adjust the desired I/O ports for Simulink and start the build process. After a while it stops with the mentioned errors. 

 

I’m quite frustrated since those steps work as long there is no “QSYS IP” involved. 

Does anyone have experience with that? Why is Quartus unable to find those specific libraries in this case? Am I wrong with my idea of this QSYS-design?
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