Smart compilation disabled by automatic script execution?

[Altera_Forum]

I recently used automatic script execution to rename the .sof file at the end of the assembly phase and now I notice that the compiler tool always starts with a new synthesis even though I have smart compilation turned on. 

 Is it supposed to work like this or must I have done something else to cause this?

[Altera_Forum]

Calling individual parts of the compile such as quartus_map, quartus_fit, etc. does not utilize smart compilation. Run "quartus_sh --qhelp" and look at the quartus_sh stuff. 

 There is an option to determine_smart_action, which it writes to a file. I've never used that before. You can also use "quartus_sh --flow compile", as that should use Smart Recompilation. Of course, it doesn't write out the .sof with the right name.  You could easily just change the name in Tcl "file copy " or re-run the assembler command line after the final flow, so you'd end up with two .sofs, one with the correct name.

[Altera_Forum]

--- Quote Start ---  Calling individual parts of the compile such as quartus_map, quartus_fit, etc. does not utilize smart compilation. Run "quartus_sh --qhelp" and look at the quartus_sh stuff.  --- Quote End ---   I'm not calling any of these. I'm using post_module_script_file (http://www.altera.com/support/examples/tcl/auto_processing.html) to do a rename in tcl at the end of the assembly phase. I start compilation from the GUI as usual.  What I mean is, is smart compilation automatically disabled as soon as you start using the triggers. I can think of reasons why Altera would decide to always do full compilation when tcl scripts are involved, because there is no way to tell what a tcl script does for each phase and if it has to be rerun. On the other hand in my case it is just annoying and not at all useful.

[Altera_Forum]

Interesting. It definitely seems like incorrect behavior, and you might want to file an SR. 

 If you want a "Not-so-smart" recompilation, go to Assignments -> Design Partitions. If you're not using partitions, one still exists called Top, which is essentially your top-level. Just change the netlist type to Post-Synthesis, and it will skip synthesis, or post-fit to skip the fitter. Actually, since it's user controlled, it actually is Smart, but you have to remember to change it back. Not ideal, but might save some time.

[Altera_Forum]

One other thought is to add the Tcl script as a button to the GUI. It's pretty easy. Tools -> Customize -> Toolbars and add the Tcl toolbar. Then Tools -> Tcl and you can link a Tcl button to a particular script. Still a manual step at the end, but not too bad.

[Altera_Forum]

--- Quote Start ---  One other thought is to add the Tcl script as a button to the GUI. It's pretty easy. Tools -> Customize -> Toolbars and add the Tcl toolbar. Then Tools -> Tcl and you can link a Tcl button to a particular script. Still a manual step at the end, but not too bad.  --- Quote End ---    To give you an idea of what I am using this for, I have the tcl script look for a node in the post-fitting system to see which out of two VHDL files was compiled. The advantages of this are: - I can share all Quartus settings, timing constraints and SOPC files - I won't have to duplicate all of the above and keep them in sync - HDL designer, which I am using to produce the VHDL, is the only place I need to deal with which configuration I am building - there is no risk of people thinking a .sof file was built from one design while it was really built from another  I'll consider the button if I cannot find another solution and people really want to use smart compilation. Thanks for the suggestion.

[Altera_Forum]

A final thought... You have some way the user "chooses" which VHDL file to use, whether it be a configuration statemet, or you're just adding/removing a different file. Maybe you could use revisions, whereby one revision adds file A and writes out a .sof called fileA.sof(or whatever name makes sense) and another revision for file B. The revision is listed at the top of the Quartus II project, so the user is less likely to be confused, and since they're already doing something to switch what file is used, that might be a good solution.

[Altera_Forum]

--- Quote Start ---  A final thought... You have some way the user "chooses" which VHDL file to use, whether it be a configuration statemet, or you're just adding/removing a different file. Maybe you could use revisions, whereby one revision adds file A and writes out a .sof called fileA.sof(or whatever name makes sense) and another revision for file B. The revision is listed at the top of the Quartus II project, so the user is less likely to be confused, and since they're already doing something to switch what file is used, that might be a good solution.  --- Quote End ---    The problem with that is that each revision gets its own settings file (.qsf). I'd have to keep those in sync, which is something I am trying to prevent. Also the selection for which VHDL is generated is done in Mentor Graphics' HDL designer, not in Quartus, so we'd still be doing a selection in two places.

[Altera_Forum]

If you can, please file a Software Request about Smart Recompiling not working. I really thing these Tcl scripts should be used more. (The thing I'd like to do is a pre-processing script, i.e. more intelligence in a .tcl file that makes assignments to your .qsf before each compile. This allows a lot of cool things. For example, one file with two pinouts(for two boards) and a single setting lets the user decide which pinout to use. True-scripts for assignments(like for-loops), etc.))

[Altera_Forum]

Yeah, that would be great. I was sorry to find out that there were only post-module hooks. I wanted to trigger the build of a bootloader at the start of the assembly phase, because it is stored in the boot-rom of the SOPC EPCS controller. But instead I'll have to check the hex file into version control, because my colleagues probably don't want to do any command line stuff.  

This is also why creating a makefile structure and starting synthesis/fitting/etc from there is not an option.  I'll create a SR tomorrow and will let you know what they say.