Source Synchronous mode in different quartus version

[Altera_Forum]

hi, everyone, 

I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment.  When builded with Quartus 9.1, the "rx" input register was placed in the fast io register as expected.  But when builded with Quartus 13.1, a warning showed  "Warning (15062): PLL "altpll0:inst|altpll:altpll_component|altpll_s6m2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register"   and the input register connected with "rx" was not placed in a fast io input register. TimeQuest report also have a 3ns skew.    why this happened?  thanks   JHH

[Altera_Forum]

Did you regenerate the IP when you switched versions? Or did you throw the old IP at the newer tool? If so, try regenerating the IP. 

 If you did regenerate the IP - and you're sure it's parameters are like for like - then differences in behaviour like that, between Quartus versions, should certainly be put to Altera. Raise a ticket via mysupport (https://mysupport.altera.com/alteraservreq/mysupporthomeclassesview.html).  Cheers, Alex

[Altera_Forum]

What's your FPGA family? With Cyclone III/IV, I see always fast input registers used for serial links. No change in Quartus 13. 

 Frank

[Altera_Forum]

I tried regenerating the IP, it didn't make any difference.

[Altera_Forum]

I see that sfr_reg[1] is implemented as fast input register in Quartus 9. sfr_reg[0] is however not fed by an input pin and can't be implemented as fast input register. I wonder how the compensation for the common clock is expected to work in this case. 

 You can make sfr_reg[1] a fast input register by an explicit assignment in Quartus 13. But the compensation problem will probably persist.