Storing 8 bit data in SDRAM in DE 0 Nano

[Altera_Forum]

Hello, 

 I want to do high speed data acquisition (50 Msps approx.) with my de 0 nano board. I need to store 8 bit data samples in it and transmit it. Though i have managed to perform uart I am not sure as to how to proceed for storing my samples in sdram.  Thank you

[Altera_Forum]

You could consider writing your own SDRAM controller... 

 However, I suggest you get to grips with Altera's SDRAM Controller Core IP. See chapter 2 in the "embedded peripherals ip user guide (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahukewius5mi48rnahxf5xokhzssapqqfggcmaa&url=https%3a%2f%2fwww.altera.com%2fen_us%2fpdfs%2fliterature%2fug%2fug_embedded_ip.pdf&usg=afqjcnfejbjdttj8ylq-5l5g1dl_nah9cw)". You'll probably find writing rtl to control Altera's Avalon interface much more straightforward than writing a complete SDRAM controller.  Cheers, Alex

[Altera_Forum]

Thank you for your reply,  

Is it possible to make a vhdl programme for the above stated purpose ?

[Altera_Forum]

Hello Tejas,  

 There is a nice tutorial: Using SD ram on DE0 Nano from Altera university.  ftp://ftp.altera.com/up/pub/altera_material/15.0/tutorials/verilog/de0-nano/using_the_sdram.pdf  I used to get started with the SDRAM.  ps: You might need a separate PLL get the timing of the FPGA and the SDRAM in line. This is at the end of the tutorial, but very important.   Good luck, Johi.

[Altera_Forum]

Yes, you can connect the SDRAM Controller Core IP directly to your VHDL. Generate the rtl through Qsys and instantiate it, using the generated module template, in your VHDL. 

 Cheers, Alex