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Strange behavior of Actions in State Machine Wizard with registered output

GeraldLi1
Beginner
1,214 Views

Hello,

I use Actions in State Machine Wizard with registered output

This output is OK if I give level (0 or 1) to each State

see attached pdf file

is this behavior correct ?
did i forget something ?

Thanks

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7 Replies
RichardTanSY_Intel
1,173 Views

It is a bit difficulty to understand the problem without looking at the code.

Could you share the design code of these two designs?

Btw, what is "canal" mean here? I never seen this tool before.

Would be appreciate if you could help to clarify on this.


Best Regards,

Richard Tan


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sstrell
Honored Contributor III
1,168 Views

I think "canal" is "channel."

Yeah, seeing the code output from the State Machine Wizard would be helpful.

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GeraldLi1
Beginner
1,154 Views

Hi

your State Machine Wizard store level 0 between States but NOT level 1

I use Arduino Vigor board

See attached files & photosBad.jpgSM_OK.jpg

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RichardTanSY_Intel
1,138 Views

Sorry for the delay in response.

I believe from design functionality, they are different.

You may check from the RTL viewer that both design function different. The SM output is from State 2 (bad) vs state 1 (OK).

My recommendation would be to simulate the design first in order to verify that you get the desired function.

RichardTanSY_Intel_0-1675911143519.png

 

Best Regards,

Richard Tan

 

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RichardTanSY_Intel
1,101 Views

May I know does my latest reply helps?

Do you need further help in regards to this case?


Best Regards,

Richard Tan


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RichardTanSY_Intel
1,084 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. I now transition this thread to community support. 


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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GeraldLi1
Beginner
1,073 Views

I have developped this Logic Analyzer based on Arduino Vidor WITHOUT Verilog knowledge !
https://gelit.ch/Vidor/LA_E.pdf
https://github.com/gelit/Logic-Analyzer-with-Arduino-Vidor

it was possible because Intel Quartus Lite provides higher level abstraction with graphical tools like Block Diagram/Schematic & State Machine File

My proposal is to modify State Machie Wizard allowing user to edit only page 5 of https://gelit.ch/Vidor/LA_E.pdf
- every output will be initialized
- ONLY output change MUST BE WRITTEN

Have a good day / retired IT professor Gerald Litzistorf - https://gelit.ch/

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