Stratix 10 Example Design Pin Assignment issue

covfefe · ‎01-13-2023

Hello,

I have a Stratix 10 GX Dev Kit (DK-DEV-1SGX-L-A, 1SG280LU2F50E2VG), and want to get a working example of the High Speed Transceiver links.

I was able to find a 2020 example project made by @Peter_S_Intel : S10_SIBoard_LVDS_4Ch_HW_Demo_V23032000

I am able to compile it without issues (Quartus 21.4 Windows 10) out of the box.

I was hoping to compile it, and assign the lvds_tx pins to the FMC connector, and then monitor the link performances with lab tools (oscilloscope, eye diagram, logic analyzer, etc).

However, once I start assigning pins (ex: PIN_AP1) to lvds_tx[0:4] in Quartus, I run into error messages that abort the compilation, example:

Error(14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. 
	Error(175020): The Fitter cannot place logic pin in region (276, 97) to (276, 98), to which it is constrained, because there are no valid locations in the region for logic of this type. 
		Info(14596): Information about the failing component(s): 
			Info(175028): The pin name(s): lvds_tx[0] 
		Error(16234): No legal location could be found out of 2 considered location(s).  Reasons why each location could not be used are summarized below: 
			Error(175005): Could not find a location with: LVDS (2 locations affected) 
				Info(175029): AP1 
				Info(175029): pin containing PIN_AP1 
			Info(175015): The I/O pad lvds_tx[0] is constrained to the location PIN_AP1 due to: User Location Constraints (PIN_AP1) 
				Info(14709): The constrained I/O pad is contained within this pin

I have tried a number of pins, all result in similar errors that I fail to understand.

See attached .qar file (which is basically the demo example provided + the pins assigned in the screenshot)

Nurina · ‎01-17-2023

Hello,

Since this issue is related to devkit, can you repost this thread to the FPGA, SoC, And CPLD Boards And Kits Community?

Thanks,

Nurina

Nurina · ‎01-18-2023

Hi,

We do not receive any response from you on the previous question/reply/answer provided, so I shall close this case.

Regards,

Nurina