Stratix 10 GX EMIF IP corrupting Host Boot code

[SivaKona]

Hi 
While my SOF files with PCIe EP alone work fine, The SOF file with PCIe EP and EMIF instance corrupt BOOT Flash of Host and cause a hang on the Host machine.

Need your expert inputs to debug this issue. 

Regards

Siva Kona

[wchiah]

Hi,

Can you clarify more how the corruption happen?

Is there any error code ? Printscreen will be helpful.

I found a related issue on corruption as well, feel free to take a look, hope this can help you.

• https://community.intel.com/t5/FPGA-Intellectual-Property/PCIe-Inbound-Byte-write-data-corruption-SolutionID-rd04172014/td-p/113080
• https://community.intel.com/t5/Processors/Uefi-system-is-corrupted-due-to-failed-start-with-a-SSD-and-Uefi/m-p/1318499/highlight/true

Regards,

Wei Chuan

[wchiah]

Hi,

I wish to follow up with you about this Forum case.

Is there any feedback from the previous reply ?

Regards,

Wei Chuan

[wchiah]

Hi Mr Siva,

I believe this case had route to internal expert.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

I would appreciate taking a moment to fill out the short survey with regards to your experience using Intel Forum Support.

If our support score is less than 9/10, I will value any feedback you can provide.

Regards,

Wei Chuan

[SivaKona]

Hi Wei Chuan,

Thank you for your inputs.

Can this post be assigned to DDR support team?

This issue is not yet resolved and we are looking for some ways to debug this further. 

Regards

Siva Kona

[wchiah]

Hi Siva,

Can you try below method

1. When failing occur, reset the controller to let it re-calibrate at that temperature.
2. If this helps, it could be due to calibration margin is not sufficient to adapt for temperature change.
3. Reduce interface frequency. Probably reduce to 200MHz or the lowest 125MHz that support for DDR controller.
4. Upgrade the quartus to latest version. I will suggest give it a try on Q22.2.
5. Measure voltage supply like VCCIO, VCCPD, VCC, VCCA_PLL, VTT, VREF.
6. See if the voltage range is operate within the specification stated in DataSheet
7. As this is board to board variation issue, have you tried to swap the device between good and bad board? See if the failure is follow the board or follow the device.

Regards,

Wei Chuan

[AdzimZM_Intel]

Hi Siva,

May I know the details of EMIF IP corrupting Host Boot code?

Would be helpful if there are some screenshots of the situation.

Is there any timing violation occur in the design?

Have you tested the EMIF IP alone on the board?

Regards,

Adzim

[SivaKona]

Hi Adzim,

Following are the EMIF Interface Configuration steps that we followed.

1. Instantiate “External Memory Interfaces Intel Stratix 10 FPGA IP” from “Memory Interfaces and Controllers” library of IP Catalog
2. Applied “Stratix 10 GX H-Tile FPGA Development kit with DDR4 HiLo” Preset as shown in Snapshot “preset_cfg_changes_1.png”
3. Exported pll_ref_clk with name ddr_ref_clk
4. Specified connection from “rxm_bar0” of PCIe EP instance to “ctrl_amm_0” of “emif_s10_0” instance. And Tool identified two Errors
1. Error: gyann_fpga.emif_s10_0.ctrl_amm_0: Data width must be of power of two and between 8 and 4096 
5. To overcome the Error, we switched to Controller Tab and set “Enable Error detection and Correction Logic with ECC” in “Configuration, status and Error handling” sub tab.
1. This setting changed the Avalon amm Data width from 576 to 512
6. Data corruption Warning
1. Warning: gyann_fpga.pcie_s10_hip_avmm_bridge_0.rxm_bar0/emif_s10_0.ctrl_amm_0: emif_s10_0.ctrl_amm_0 does not have byteenables. Writes from narrow master pcie_s10_hip_avmm_bridge_0.rxm_bar0 may result in data corruption
7. To overcome the Warning, we switched to “Memory” Tab, to reset “Write DBI” and set “Data mask” in “Topology” sub tab
1. Setting Data mask along with “Write DBI” threw Errors

No timing violations are seen in the Build reports.

We have not tested the EMIF IP standalone, We are working to try that after your suggestion. 

We have captured videos of Successful reboot and failed reboot scenarios. During the failure, The Host just Shuts down and does not Power up at all.

I will share the videos if required over email. 

Regards

Siva Kona

[AdzimZM_Intel]

Hi Siva,

You can use EMIF example design for the test.

Please ensure that you've provided a stable reference clock to the EMIF IP block.

Please let me know the result of the test.

Thanks.

[AdzimZM_Intel]

Hi Siva,

May I know any update on your testing?

Thanks.

-Adzim

[AdzimZM_Intel]

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.