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Stratix 10 HPS DDR4 EMIF placement error

GMcCa2
Novice
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Hello,

I'm trying to compile a design for the Terasic S10 SOM (https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=248&No=1229&PartNo=1#contents).

They provide a GHRD which I am able to compile on Quartus 19.1. I am now trying to compile it on Quartus 24.1 and get the following error:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IO_LANE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
    Error (175020): The Fitter cannot place logic IO_LANE that is part of External Memory Interfaces for HPS Intel Stratix 10 FPGA IP emif_hps_altera_emif_s10_hps_1928_3oj4n7y in region (61, 1) to (61, 400), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The IO_LANE name(s): soc_inst|emif_hps|altera_emif_s10_hps_inst|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[2].lane_gen[1].lane_inst|lane_inst
        Error (16234): No legal location could be found out of 1 considered location(s).  Reasons why each location could not be used are summarized below:
            Info (175013): The IO_LANE is constrained to the region (61, 1) to (61, 400) due to related logic
                Info (175015): The I/O pad DDR4A_BG[1] is constrained to the location PIN_D40 due to: User Location Constraints (PIN_D40)
                Info (14709): The constrained I/O pad drives a TILE_CTRL, which drives this IO_LANE
            Error (175005): Could not find a location with: HPS_DATA_LANE_RESERVATION_ID of HPS_LANE (1 location affected)
                Info (175029): IO12LANE_X61_Y327_N2

When upgrading to 24.1 it forces an IP upgrade on the HPS EMIF IP, so could be related to that. I looked through the parameters and everything seems to match the original values after the upgrade.

I am hoping to get 24.1 working, as I have multiple IP files that are shared with other projects that won't work on 19.1.

I've attached an archive of the project I was able to compile in 19.1.

Thanks for any help you can provide.

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khtan
Employee
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Hi,

Thanks for using Intel Forum, I'm Kian and will be assisting in this case. Let me check on our database and the design and will get back to you later. 

 

Thanks

Regards

Kian

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khtan
Employee
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Hi,

Sorry for the delay in getting back to you. Just a status update on my investigation side, unfortunately still have issues on the pin placements

 

1. Able to replicate the same observation as you posted in the thread.

2. Found out that there is a KDB on this issue (https://www.intel.com/content/www/us/en/support/programmable/articles/000086902.html)

Apparently Quartus 19.1 and below have issues on the pinout restriction detection thus compilation will always pass.

 

What have been tested so far

1. Multiple Quartus version (20.1, 23.1, 24.1) to test the fitter to see any differences on the issue. All result with the same error.

2. Check the pins that are mentioned in the KDB (PLL and RZQ) and looks like it is already in bank 2M. Suspect other pin placement restriction.

3. Terasic website on newer designs able to compile on 24.1 but without EMIF HPS or the GHRD project (tested few designs) 

3. Remove all pin assignments for DDR4A and let fitter to decide which pins to utilize . Result in different error where fitter unable to fit all the pins with the region constraints.

4. Manually remove pin assignments that were reported error by fitter tool and let fitter reassign the pins during compilation each time but eventually fitter still fails in the assignment.

 

Ongoing:

1. Looking at the pin placement restriction based on the KDB documentation and comparing to the Terasic user manual.

2. Engaging with EMIF expert to check on the DDR pin placement

 

Thanks

Regards

Kian

 

 

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GMcCa2
Novice
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Thanks for the update. I emailed Terasic support about this and they mentioned that they were able to compile with 19.4. Thought that might be relevant since the KDB you mentioned was fixed in 19.2.

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khtan
Employee
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Hi ,

Sorry for the delay in getting back, was scrutinizing the pins with the team and doing testing on the Quartus fitter

 

To resolve the fitter error on the IO lane and tile,  you will need to remove the pin assignment CLK_50_B2L in pin planner and let the fitter reassign it automatically  (alternatively edit the qsf file, and remove the constraint "set_location_assignment PIN_BA27 -to CLK_50_B2F"

 

 

khtan_1-1719020730190.png

 

This is some others restrictions that was put in place in the requirements on banks 2M, 2L, 2N (other than the ones mentioned in the KDB )

khtan_2-1719021693566.png

 

On quartus 19.4 , probably I will check it later , as the KDB mention 19.1 and below, but i suspect additional requirements been put in place as well.

 

Thanks

Regards

Kian

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