We are using stratix 10 SoC kit. We enabled HPS along with DDR4 & Transceiver blocks. In quartus, we have set the "FPGA first configuration" mode (AFTER INIT_DONE). After that, generated the sof & merged fsbl with sof using "quartus_cpf" command as mentioned in the below link
Then the merged sof is programmed successfully. After that, we want to monitor soe signals through signaltap. When I open the signaltap, it is asking for reprogram FPGA. Also, in the system console of quartus, Error message is showing that JTAG ID is not matching.
Recompiled with Same project with commented HPS instantiation. With this sof is programmed & able to see the DDR4 calibration status & transciever calibration status through JTAG.
So, I am seeing the issue with signaltap when HPS is enabled. Whether this is known issue & any work around is suggested for this kind of behaviour?