Hi,
I am trying to instantiate a transceiver I designed for Stratix V. Here is module declaration:
module optic_xcvr_mod(
input wire system_clk,
input wire pll_ref_clk,
input wire rx_serial_data_0,
output wire tx_ready,
output wire rx_ready,
output wire tx_serial_data_0
);
...
And here is the instantiation within the top level design file:
wire system_clk_0;
wire pll_ref_clk_0;
wire rx_serial_data_0;
wire tx_ready_0;
wire rx_ready_0;
wire tx_serial_data_0;
optic_xcvr_mod xcvr_mod_1(
.system_clk(system_clk_0),
.pll_ref_clk(pll_ref_clk_0),
.rx_serial_data_0(rx_serial_data_0),
.tx_ready(tx_ready_0),
.rx_ready(rx_ready_0),
.tx_serial_data_0(tx_serial_data_0)
);
Yet I keep getting the error "REFCLK port on the PLL is not properly connected on instance...". I assume it is talking about the pll_ref_clk, which from what I can tell is connected properly.
Thanks in advance for your help
