Stratix V pin I/O delays

[Altera_Forum]

Hi  

I am currently trying to build a board with some DDR3 memory on, and for that I need the PIN I/O delays so I can do external Deskewing.   but I can't figure out how to generate this pin delay list,  I am using Quartus 14.0  I have tried using https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/external-memory/emi_plan.pdf but that did not make me any wiser.  Any help will be much appreciated.  /Rasmus

[Altera_Forum]

Hi, 

 What is the pin delay list that you are looking for? Is it a list of delay for different settings?

[Altera_Forum]

One alternative is to configure the IO delays in your design and run through Fitter compilation. The Fitter report should have the delay values for different settings.

[Altera_Forum]

I am looking for the internal delay of each pin. in Xilinx I can just draw a list. 

This should be a constant for that version of my chip. I don't see why I need to configure any design for this?

[Altera_Forum]

Page 4-41 of the doc you posted list exactly how to do it. Unfortunately Altera does not provide a document that list pin delays for every pin/device combination. You must compile the design with the board deskew option turned on to get the package delays to show up in the pin report. 

 To get the package delay information, follow these steps: 1. Select the FPGA DQ/DQS Package Skews Deskewed on Board checkbox on the Board Settings tab of the parameter editor. 2. Generate your IP. 3. Instantiate your IP in the project. 4. Run Analysis and Synthesis in the Quartus Prime software. (Skip this step if you are using an Arria 10 device.) 5. Run the <core_name>_p0_pin_assignment.tcl script. (Skip this step if you are using an Arria 10 device.) 6. Compile your design. 7. Refer to the All Package Pins compilation report, or find the pin delays displayed in the <core_name>.pin file.