Stuck clock

Altera_Forum · ‎10-30-2011

Hi all, I'm trying to build a microprogrammed computer, but get problems

when I try to implement the bus.

"Warning (14110): No clock transition on "sram:SRAM1|addr_reg[0]" register due to stuck clock or clock enable"

I get several of these, but they disappear if I comment out the last line

with the assignment to sram_address. Have I made an error?

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity sram is
    port(reset, clk : in std_logic;
         sram_address : out std_logic_vector(17 downto 0);
         sram_data : inout std_logic_vector(15 downto 0);
         sram_ub_n, sram_lb_n, sram_ce_n : out std_logic;
         bus_line : inout std_logic_vector(15 downto 0);
         addr_r, dq_r, dq_w : in std_logic
        );
end sram;
architecture arch of sram is
    signal addr_reg : std_logic_vector(15 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '0' then
            addr_reg <= (others => '0');
        elsif rising_edge(clk) and addr_r = '1' then
            addr_reg <= bus_line;
        end if;
    end process;
    
    bus_line <= sram_data when dq_w = '1' else (others => 'Z');
    sram_data <= bus_line when dq_r = '1' else (others => 'Z');
    
    sram_ub_n <= '0';
    sram_lb_n <= '0';
    sram_ce_n <= '0';
    
    sram_address(17 downto 16) <= (others => '0');
    sram_address(15 downto 0) <= addr_reg;
end arch;

I can show you the code where I instantiate this entity, if it matters.

Altera_Forum · ‎10-30-2011

You are using the SRAM in 16bit mode.

As you are reading 2Bytes at once, there is no need to address odd bytes.

Therefore, on 16bit access, the lowest address line is not used.

This is also true for other types of memory like flash, SDRAM etc.

Also, there should be no pin on the RAM device for this address line, anyway.

Altera_Forum · ‎10-30-2011

I use the IS61LV25616 with the DE2 board, the datasheet says it's organized

as 256k * 16 bits. It has 18 address lines, and 2^18 * 16 bits is 512kb which

is the number printed on the board. This means that every address must be used, even odd ones. Are you thinking about some other memory?

Altera_Forum · ‎10-30-2011

As NIOS sees you are adressing the memory in 16 bit mode, it will not toggle the lowest address line.

Most memories have a means of switching between 8bit and 16bit access, where one would need the lowest address line. That's why it is created whatsoever.

Your memory is fixed to 16bit, so the lowest address line (sometimes they even call it A-1) seems to be omitted already on the device.

From that, I would think you might need another address line (a nineteenth one).

i would think, with 18 address lines the nios system allocates only 256kb of space, not 512kb; you should check it in the address map.

Edited: Forget this sentence. As you are conecting the SRAM directly to the bus, it will not show up in the memory map.

With that in mind, you can safely ignore warnings about the stuck A0 line and try accessing the device. Be prepared to try and fiddle with the address lines a bit before you get valid results. Maybe you even need to change the code for the device. I had these problems when getting a parallel flash to work, which uses the same interface.