Support for multiple instances?

[AEsqu]

Hello,

With Vivado there is not problem to handle this situation:

The main RTL is synthesized in one vqm.

Then a small top level is synthesized with Synplify,

it instantiates the main level two times (as black boxes).

The 3 VQM are provided to Vivado which places the two main instances and the top without problem.

Now, with Quartus 21.1 pro, this is not working, it sees duplicated modules (as the same VQM for the main is used, this is expected).

Would it be possible for Quartus in the future to support that scenario,

by looking at the full instance path instead of per block?

Thanks,

Alex.

[sstrell]

What exactly "is not working"?  Compilation failure?  What errors are you getting?  Are the two instances of the same block uniquely named?  Quartus Standard or Pro?  Way more info needed here.

[AEsqu]

You apparently did not read the original post properly.

Please read it again, not just the title.

[sstrell]

I did read the whole post.

When you simply say something is not working, that doesn't explain what the issue is.  And if there are any warning or error messages, that helps someone clue in on what the problem is.

And as far as duplicate naming is concerned, you don't mention that in your original post, so I asked.

[Kenny_Tan]

Hi Alex,

Would you mind including the design.qar for us for the investigation? This will accelerate the feature request process.

Kindly note that there will be some slowness on the first reply due to the public holiday, we will get back to you as soon as possible.

Thanks

[AEsqu]

Hello Kenny,

I will try to create a small test case for you,

I cannot share my current design.

Edit: Please write me an email Kenny,

I will reply to you with a sharepoint link to download the test case,

I used the same way with your colleague Syafieq for another test case (Case #: 05796098) and he could download it.

Kind Regards and Happy Holiday,

Alex.

[AEsqu]

Ok I have the test case ready.

Please find below 3 possible situations:

A: The blocks have the same name, the same functionality and the same interface,

Quartus issues a warning and proceed, the synthesis will be correct.

Picture: duplicated_ignored_warning_when_io_and_functionality_is_matching.png

B: The blocks have the same name with the same interface but different functionality,

Quartus issues a warning and proceed, the synthesis will be Incorrect.

C: The blocks have the same name but different functionality and different interface,

Quartus issues an error.

 Picture named duplicated_ignored_error_when_blocks_have_different_function.png

[AEsqu]

Hello 

Qi sheng N.,

Can you confirm that you were able to load the file via sharepoint (see email)?

Thanks,

Alex.

[ShengN_Intel]

Hi,

I also got similar synthesis error in Vivado tool both version 2021.1 and 2022.2. Check image below.

The synthesis only can pass if the module name is different for example by changing either one to HV45_O25_CNHLSX4v2. Same thing goes for Quartus. Check image below.

Because if the module name is same but context of the modules are different , it'll be overwritten which caused the issue. If the module name is same and context of the modules are same as well then should be no problem even overwritten.

Check this previous forum case https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-handle-multiple-files-with-the-same-name/td-p/722787, I believe Quartus can't support synthesis of multiple RTL files with same name but context of the files are different.

I had sent the fail and pass .vqm files to your email privately.

Thanks,

Best regards,

Sheng

[AEsqu]

Ok if Vivado behaves the same, we can close the topic then.

I was just wondering why you were sending back the test cases I provided to you Sheng.

Kind Regards,

Alex.