Suppress Warnings like 14110

[Altera_Forum]

Eploring a new design, I find (among others) warnings like this : 

 Warning (14110): No clock transition on "pcie_top_4x125:pci .... register due to stuck clock or clock enable"  which I would like to shun by excluding them with an "always off" command in the compiler settings tab. Somehow, Quartus dos not accept these numbers with 14xxxx.  What can I do ?

[Altera_Forum]

It sounds like you're saying you tried to suppress them using the "Advanced Message Settings" dialog box accessed from Analysis & Synthesis Settings. It would be good to file a service request for that not working. 

 You should be able to suppress them by right clicking one of the messages and using "Suppress --> Suppress All Similar Messages".

[Altera_Forum]

Right, i used dialog box as described. For some reasons, Quartus does not accept to stop them from withn this box. 

 But the right-mouse-click advice worked, thanks. Where does Quartus store this setting to suppres certain messages ?

[Altera_Forum]

I think, into the file .SRF, but I strongly recommend to use the GUI interface called Message Suppression Manager in Quartus II to manage the messages.

[Altera_Forum]

I still get an error "HDL message ID illegal, enter 10000 ... 11000" from the GUI.:confused:  

 With the message suppression manager, it works.:)

[Altera_Forum]

In the current version of Quartus II, the advanced message settings dialog only controls messages that are generated during the Analysis & Elaboration of your Verilog and VHDL. These messages are called hdl messages and have IDs between 10000 and 11000. Quartus II generates Message 14110 during logic optimization. I wouldn't be surprised if the next version of Quartus II allows you to suppress all Message IDs in the Advanced Message Settings dialog.  

 Are you sure you want to suppress that warning globally? Having a register with a stuck clock or enable sounds pretty scary! Is this warning coming from your own design logic or IP?   Josh

[Altera_Forum]

Right, but at the moment the design is that "open" that there are hundreds of useless warnings, which will disappera anyway after additional modules will be included. 

 Furthermore : I am using the "clock off" - method to dynamically remove parts of a design which I do not need for a certain test to be able to add also Signal Tap Logic and much RAM.

[Altera_Forum]

I see your point. Are you actively using Incremental Compilation? You can also dynamically remove parts of your design or account for missing modules by setting the corresponding hierarchy as a design partition with the Netlist Type to Empty. This would also eliminate many of those synthesis warnings.