We use Block diagrams to be able to understand the architecture of our quite large systems. These allow us to easily see the connectivity between multiple processors, memories, digital filters, and other processing blocks in our design. This kind of connectivity is very hard to fathom from text only Verilog files.
Up to Quartus 12.1 the symbols generated by Qsys and the Megawizards were flow based with inputs on the left and outputs on the right, with names as assigned by the user. The symbols could also be made quite compact.
With Quartus 13 and on the symbols are much larger, have huge port names that repeat the name of the module they are in, have two names per port - the wire name and the name in the rectangular outline which is often meaningless - such as 'conduit'. As well as that symbols are no longer flow based, and have all pins on one side until they eventually flow over to the other side. The user is not ale to define the entire name.
We can no longer make meaningful block diagrams. This is terrible!
We urge Altera to have an option for old style symbols. Just in case there is such an option, does any one know what it is?
If you also find the new symbols horrible, please chime in. I have no idea why Altera wanted to break this system which was working nicely.
