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14964 Discussions

Synthesis Hung for Large Designs

apducimo
Beginner
935 Views

I am trying to synthesize a design that includes:

  • 64x64x64x128 Single-Port RAM
  • 64x64x64x32 Single-Port ROM
  • 64x64x64x64 Two-Port RAM

on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have found that the tool is stuck at 33% of the Analysis & Synthesis phase for 3 days. There are no meaningful warnings about the RTL design and I believe I have enough resources on the device for this design.

For what it's worth, I was able to implement both a design that includes:

  • 16x16x16x128 Single-Port RAM
  • 16x16x16x32 Single-Port ROM
  • 16x16x16x64 Two-Port RAM

and a design that includes:

  • 32x32x32x128 Single-Port RAM
  • 32x32x32x32 Single-Port ROM
  • 32x32x32x64 Two-Port RAM

See attached PNG, it summarizes some of the results for both the successfully implemented designs.

I was running into a similar issue before, but the tool ended up synthesizing the design (albeit a slightly different one) in 30 hours, it then took 4 hours to get through Timing Analysis. Unfortunately, I no longer have information from that run.

0 Kudos
23 Replies
RichardTanSY_Intel
769 Views

Sorry for idling for some time. Do you able to solve the issue? 

Have you try to the design with another computer?
Try and reinstall the latest Quartus Pro 20.4 to see if the issue persists. 

apducimo
Beginner
766 Views

Yes I have tried on multiple machines each with their own installation of Quartus Pro 20.4. I even tried earlier version of Quartus Pro and git the same issue. I only update to Quartus Pro 20.4 to prevent the request to run with the latest version of the tool

 

RichardTanSY_Intel
742 Views

Could you help to share your design so I could test it from my side? 

apducimo
Beginner
727 Views

Working on it. I am trying to reproduce a logfile to accompany the design inputs.

apducimo
Beginner
711 Views

I have attached all necessary design files and the output files resultant of running synthesis.

The output files were generated using Quartus 18.1, with synthesis stuck at 33% after 11 hours. I will let it go until my allotted 72 hours have expired on the machine this process in running on.

Though these reports are generated with 18.1, you should be able to reproduce the issue with 20.4.

Let me know if you run into any issue trying to retrace this issue on your end or if you need any other files from the Quartus run.

apducimo
Beginner
692 Views

I have updated logs but I the sizes of files exceed the attachment limitation. Let me know how to transmit the updated reports.

RichardTanSY_Intel
682 Views

I think you could transfer the file through FTP.

Is the top level file - wrapped_md_lr_top.sv ? I try to compile then error out:

Error(16827): Verilog HDL error at wrapped_md_lr_top.sv(120): cannot open include file ../tb/include/particle_info.svh

Could you help to check for this missing file and help to attach? 

apducimo
Beginner
676 Views

It is not. md_lr_top is the top file. I believe all the information you need to build the design is in the log file, but ask away with any questions you have.

RichardTanSY_Intel
665 Views

May I know how much is the memory RAM in your PC/machine? 

apducimo
Beginner
661 Views
apducimo
Beginner
660 Views

I did attempt runs on machines with insufficient RAM size and I received an error message indicating that was the case.

RichardTanSY_Intel
644 Views

I also got the same error message with insufficient RAM size. I not sure if we have a machine with enough RAM memory to run this design as our server will kill the Quartus if exceed memory usage.
last I know it use up to 160 GB before it got killed.

Would it be possible for you to change the device to other devices e.g. Arria10 with lesser memory usage? 

apducimo
Beginner
639 Views

I don't believe the Arria10 has enough BRAM bits to support the size of the design.

RichardTanSY_Intel
626 Views

I encounter below error, do you have this error before?

Error(13305): Verilog HDL error at md_lr_top_64x64x64.sv(254): can't find port "user_reset" 



apducimo
Beginner
619 Views

No. I was not seeing this error. From the sounds of it, you are not using the IP as I delivered it. Perhaps you have upgraded it to the point where the IP no longer has the pins that it once had.

RichardTanSY_Intel
585 Views

I have ask the engineering to check on this abnormal behavior. Will let you know once there is update.


apducimo
Beginner
579 Views

So you were able to recreate the issue, correct?

RichardTanSY_Intel
577 Views

Yes, I am able to duplicate the issue with Quartus stuck at 33% Analysis & Synthesis stage.

RichardTanSY_Intel
523 Views

You mentioned previously that you are able to implement design with 

16x16x16x128 Single-Port RAM
16x16x16x32 Single-Port ROM
16x16x16x64 Two-Port RAM

and

32x32x32x128 Single-Port RAM
32x32x32x32 Single-Port ROM
32x32x32x64 Two-Port RAM

Could you help to share the .qar design files that is able to pass the Analysis and Synthesis? Either 32 or 16 will do.  

RichardTanSY_Intel
402 Views

Do you have the .qar design for 64x64x64 as well ? Engineering need it instead of the design files zip. I am not able to achieve the project as the Quartus keep crashing. Not sure is it the same case for you. 

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