I am trying to synthesize a design that includes:
- 64x64x64x128 Single-Port RAM
- 64x64x64x32 Single-Port ROM
- 64x64x64x64 Two-Port RAM
on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have found that the tool is stuck at 33% of the Analysis & Synthesis phase for 3 days. There are no meaningful warnings about the RTL design and I believe I have enough resources on the device for this design.
For what it's worth, I was able to implement both a design that includes:
- 16x16x16x128 Single-Port RAM
- 16x16x16x32 Single-Port ROM
- 16x16x16x64 Two-Port RAM
and a design that includes:
- 32x32x32x128 Single-Port RAM
- 32x32x32x32 Single-Port ROM
- 32x32x32x64 Two-Port RAM
See attached PNG, it summarizes some of the results for both the successfully implemented designs.
I was running into a similar issue before, but the tool ended up synthesizing the design (albeit a slightly different one) in 30 hours, it then took 4 hours to get through Timing Analysis. Unfortunately, I no longer have information from that run.
Sorry for idling for some time. Do you able to solve the issue?
Have you try to the design with another computer?
Try and reinstall the latest Quartus Pro 20.4 to see if the issue persists.
Yes I have tried on multiple machines each with their own installation of Quartus Pro 20.4. I even tried earlier version of Quartus Pro and git the same issue. I only update to Quartus Pro 20.4 to prevent the request to run with the latest version of the tool
I have attached all necessary design files and the output files resultant of running synthesis.
The output files were generated using Quartus 18.1, with synthesis stuck at 33% after 11 hours. I will let it go until my allotted 72 hours have expired on the machine this process in running on.
Though these reports are generated with 18.1, you should be able to reproduce the issue with 20.4.
Let me know if you run into any issue trying to retrace this issue on your end or if you need any other files from the Quartus run.
I think you could transfer the file through FTP.
Is the top level file - wrapped_md_lr_top.sv ? I try to compile then error out:
Error(16827): Verilog HDL error at wrapped_md_lr_top.sv(120): cannot open include file ../tb/include/particle_info.svh
Could you help to check for this missing file and help to attach?
I also got the same error message with insufficient RAM size. I not sure if we have a machine with enough RAM memory to run this design as our server will kill the Quartus if exceed memory usage.
last I know it use up to 160 GB before it got killed.
Would it be possible for you to change the device to other devices e.g. Arria10 with lesser memory usage?
You mentioned previously that you are able to implement design with
16x16x16x128 Single-Port RAM
16x16x16x32 Single-Port ROM
16x16x16x64 Two-Port RAM
32x32x32x128 Single-Port RAM
32x32x32x32 Single-Port ROM
32x32x32x64 Two-Port RAM
Could you help to share the .qar design files that is able to pass the Analysis and Synthesis? Either 32 or 16 will do.