on a 1SG280LN2F43E1VG device with Quartus 20.3 and I have found that the tool is stuck at 33% of the Analysis & Synthesis phase for 3 days. There are no meaningful warnings about the RTL design and I believe I have enough resources on the device for this design.
For what it's worth, I was able to implement both a design that includes:
16x16x16x128 Single-Port RAM
16x16x16x32 Single-Port ROM
16x16x16x64 Two-Port RAM
and a design that includes:
32x32x32x128 Single-Port RAM
32x32x32x32 Single-Port ROM
32x32x32x64 Two-Port RAM
See attached PNG, it summarizes some of the results for both the successfully implemented designs.
I was running into a similar issue before, but the tool ended up synthesizing the design (albeit a slightly different one) in 30 hours, it then took 4 hours to get through Timing Analysis. Unfortunately, I no longer have information from that run.