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Synthesis - Incorrect SystemVerilog interface parameter override

fxmelvin
Novice
605 Views

I have come across an issue where Quartus Pro (21.x) Synthesis incorrectly resolves an interface parameter to its default value rather than the value with which it should've been overridden by the interface instance. Moreover, it only seems to partially affect usage of that parameter within the interface. For example, I have a use case where an interface is declared as the following:

 

interface mem_if #( int ADDR_W = 4, int DATA_W = 1 ) ( input clk );

   localparam logic [DATA_W - 1:0] INIT_V [2 ** ADDR_W] = '{default: '1};

   logic [ADDR_W - 1:0] addr;
   logic [DATA_W - 1:0] idat, odat;
   logic                wren;

   modport mem
     (
      input  clk, addr, wren, idat,
      output odat
     );

endinterface : mem_if

 

This interface is instantiated in a top-level module to connect another module:

 

module mem_wrapper #( int ADDR_W = 5, int DATA_W = 8 )
...
   mem_if #( ADDR_W, DATA_W ) mem_if ( i_clk_a );
   mem mem ( mem_if );
...
endmodule : mem_wrapper

 

"mem" internally references its interface's ADDR_W and DATA_W parameters as well as INIT_V. In the "mem" instance shown above, ADDR_W and DATA_W are correctly overridden with the instance values 5 and 8 respectively. However, INIT_V's dimensions remain defined as per the interface's default parameter values, leading to a synthesis error when trying to access its array elements. A few additional comments:

  • It doesn't matter that INIT_V is a localparam; having it instead defined as an interface parameter leads to the same problem.
  • I've tried different ways of defining INIT_V; for example, having it as a vector (single-dimension) whose length is determined by DATA_W * (2 ** ADDR_W). This problem still happens.

In the end, this seems to be a parameter dependence issue for interface definitions. I have attached the complete source code and Quartus Pro project files of the example above, which reproduces the problem I have described; here's the error returned after synthesis (note how the reported range references the array dimensions based on the default values of ADDR_W and DATA_W):

 

Error(13224): Verilog HDL or VHDL error at mem.sv(7): index 16 is out of range [0:15] for 'INIT_V' 

 

It would be great if this could be resolved in the next release of Quartus Pro (or a patch for the current release as well) since this is such a simple use case of parameterized interfaces, which Quartus claims support

0 Kudos
1 Solution
ShengN_Intel
Employee
164 Views

Hi @fxmelvin ,

 

FYI. The bug had been fixed and implemented in Quartus Pro Edition version 22.4 internal build. Tested and worked fine check the image below:

ShengN_Intel_0-1669603545525.png

 

Kindly wait for the version release. Thank you for your patience.

 

Thanks,

Best Regards,
Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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12 Replies
ShengN_Intel
Employee
572 Views

Hi,

 

I notice you use localparam for logic INIT_V in mem_if. Try don't to use that else DATA_W and ADDR_W will be assigned with local parameter. Delete the localparam and add INIT_V to modport mem will do.

 

Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

fxmelvin
Novice
567 Views

Hi @ShengN_Intel 

 

The original code is correct SystemVerilog usage and does not have to be changed; parameter dependence is a well understood aspect of SystemVerilog, having even a dedicated section in the standard explaining how overriding the relevant parameters during instantiation implies that the final parameter value must refer to that instead of any defaults.

 

Furthermore, if I understand what you're suggesting, i.e. have INIT_V as part of the mem.sv, that's not good enough for my use case; the example shared in this post is just a minimal, reproducible example of the original problem.

 

Lastly, note that the same code is synthesized correctly by other FPGA tools like Vivado.

ShengN_Intel
Employee
560 Views

Hi @fxmelvin ,

 

I have read through your post and understand what you are asking for now. Anywhere, I'll reflect this particular problem to internal engineering for further ado. Thanks for your sharing.


Best regards,
Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

fxmelvin
Novice
558 Views

Thank you, @ShengN_Intel . I'd appreciate if you could share their feedback once you hear from them.

ShengN_Intel
Employee
555 Views

Sure, will update you on that once there is any feedback from them.

ShengN_Intel
Employee
509 Views

Hi @fxmelvin ,

 

The feature requested will be planned in version 22.3. A patch will be added to that particular version. These are the feedbacks from internal engineering.

 

Best regards,
Sheng


fxmelvin
Novice
312 Views

@ShengN_Intel This is issue hasn't been fixed in Quartus Pro 22.3.

ShengN_Intel
Employee
281 Views

@fxmelvin Here is the latest update from internal team: 

Moving this to 22.4 due to schedule. Will work with Verific to provide a fix for this.

fxmelvin
Novice
504 Views

Thank you, @ShengN_Intel 

ShengN_Intel
Employee
499 Views

Hi @fxmelvin ,

 

Most welcome!
I'll now transition this thread to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.

Thank you.

 

Best regards,
Sheng


ShengN_Intel
Employee
165 Views

Hi @fxmelvin ,

 

FYI. The bug had been fixed and implemented in Quartus Pro Edition version 22.4 internal build. Tested and worked fine check the image below:

ShengN_Intel_0-1669603545525.png

 

Kindly wait for the version release. Thank you for your patience.

 

Thanks,

Best Regards,
Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

fxmelvin
Novice
150 Views

That's great, thank you for sharing additional details @ShengN_Intel 

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