I'm trying to synthesis code where based on parameters from interface I create structure and the once again I take interface parameters. Such a case results with error:
Error(13433): Verilog HDL Defparam Statement error at top.sv(34): value for parameter "WIDTH_2" must be constant expression
I check the code in Vivado and Questa and it works well.
Please find attached source code and log from quartus.
Steps to replicate:
- Use `Quartus Prime Pro Edition 22.2.0` with any devices installed
- Create a new project, add following code to `top.sv` file.
- Set `top` as Top-level Entity
- Run `Analysis & Synthesis`
Thanks for attaching the file. I will check this with the Engineering Team. It might take some time to debug the issue, please stay tuned.
Internal latest feedback:
This issue got fixed by Verific in Aug-22 release. Yet to integrate this Verific release into Quartus.
Now, asking internal team for any workaround or patch released for this issue. Please allow some working time.