Synthesis report about inference

[FabianL]

Hello,

I know it that other synthesis tools that there are certain reports, which list what kind of logic macro blocks (e.g. RAM, FIFO, MUX, Adder) is inferred for certain HDL constructs.

I could not find anything similar for the Quartus Synthesis. Is there any option to activate this?

In which report could I find information about logic inference during synthesis?

This information is crucial for debugging and optimizing HDL code.

Thanks

best regards

Fabian

[KennyTan_Altera]

Hi,

For inference, they are certain coding style you need to refer:

https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/ram-style-and-rom-style-for-inferred-memory.html

and you can open one verilog.v file. right click and insert template -> system verilog, look for the code to infer the RAM.

You can check the report in compilation report -> fitter -> place stage -> resource utilization.

Thanks,

Best regards,

Kenny Tan

[FvM]

Hi,
inference is basically reported in <project>map.rpt file

Regards

Frank

[KennyTan_Altera]

As we transition to a new platform, this thread will be closed. Please wait for the new platform to become available if you have further question.

[KennyTan_Altera]

As we do not receive any response from you on the previous qanswer that we have provided. We shall close this thread, please wait until a new platform to be available to post your follow up question if you have

[FabianL]

Ok I guess that's all that is available.

I hoped for something more detailed, since the mentioned reports basically focus on RAM & FIFOs. Other larger logic elements like Adder Muliplexer do not show up in this report.

Thanks

Fabian