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15051 Discussions

Synthesizing design for PAC with Arria 10 GX fails

RBash
Novice
1,034 Views

I'm trying to synthesize a design for a PAC with Arria 10 GX, but get the following messages when the synthesis script finishes. Since the error message doesn't give any particular information, I don't know where to look for issues to fix. It is especially confusing because first it's printed that "Info: Successfully synthesized partition", and then it fails (although I get another variation of this for a bigger design in which the partition isn't successfully synthesized). I expect the design to use 30%-40% of the ALMs on the Arria 10 FPGA, so I doubt that the design can't fit.

 

I use Quartus 17.1, and use "afu_synth_setup" to create the build directory and then inside that directory run "run.sh". I can synthesize other designs, and even some other variations of the same design successfully, so I don't think it's an environment or software version issue.

 

What am I missing here? Any help would be appreciated.

 

Info (17049): 272433 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 247070 device resources after synthesis - the final resource count might be different Info (21058): Implemented 2341 input pins Info (21059): Implemented 2621 output pins Info (21061): Implemented 210572 logic cells Info (21064): Implemented 31456 RAM segments Info (21062): Implemented 80 DSP elements Info: Successfully synthesized partition Info: Saving post-synthesis snapshots for 1 partition(s) Error: Quartus Prime Synthesis was unsuccessful. 1 error, 1768 warnings Error: Peak virtual memory: 17417 megabytes Error: Processing ended: Mon Apr 6 08:54:36 2020 Error: Elapsed time: 00:22:31 Error: Total CPU time (on all processors): 00:36:43 Info (19538): Reading SDC files took 00:03:57 cumulatively in this process. ------------------------------------------------ ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.   while executing "execute_module -dont_export_assignments -tool syn" (procedure "synthesize_persona_impl" line 14) invoked from within "synthesize_persona_impl $synth_rev" (procedure "compile_pr_revision" line 18) invoked from within "compile_pr_revision $options(impl)" (procedure "main" line 110) invoked from within "main" invoked from within "if {($::quartus(nameofexecutable) == "quartus") || ($::quartus(nameofexecutable) == "quartus_pro") || ($::quartus(nameofexecutable) == "qpro")} { #..." (file "./a10_partial_reconfig/flow.tcl" line 1039) ------------------------------------------------ Error (23031): Evaluation of Tcl script ./a10_partial_reconfig/flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 7 errors, 1770 warnings Error: Peak virtual memory: 803 megabytes Error: Processing ended: Mon Apr 6 08:54:42 2020 Error: Elapsed time: 00:22:55 Error: Total CPU time (on all processors): 00:37:33 Quartus build failed

 

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1 Solution
JohnT_Intel
Employee
737 Views

Hi,

 

Thanks for the report file. It looks like there is a conflict on the your Quartus design where the IP name use is the same.

 

Below is the error message when Quartus Synthesis is performed. You will need to make some changes on your design so that it is not using the same file name.

Error (19021): The same file name "mm_bridge_0" is used for different IP files. The same name cannot be used for more than one IP file.

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38 Replies
RBash
Novice
306 Views

Yes, it is the latest design. I tried compiling that same project that I sent you and I face the above error. But the error isn't specific to this project, when I try other relatively big designs I get this error too, whereas smaller designs just compile fine in a matter of several hours.

JohnT_Intel
Employee
306 Views

Hi,

 

May I know if you have huge storage in your system? I observed that the report file generated is around 1GB.

RBash
Novice
306 Views

I just tried again with ~59GB of free space and same error happened again.

JohnT_Intel
Employee
306 Views

Hi,

 

Let me try to re-run everything from HLS to Quartus compilation from my side again.

 

May I know which Quartus version are you using? Many system have you tested?

RBash
Novice
306 Views

Hi,

Thank you.​ I use Quartus 18.0 for HLS compilation, and 17.1 for synthesis.

I just tested on one machine, as I don't have access to other machines with Arria 10 cards. Or do you mean how many systems I tried to synthesize? If that's the case, I tried one other system that also failed.

JohnT_Intel
Employee
306 Views

Hi,

 

May I know if you are using Quartus that is part of the Intel Acceleration Stack? The reason is that you should be using Quartus 17.1.1 with Patch 136_138.

RBash
Novice
306 Views

I am using the Quartus version that's part of the Intel Acceleration Stack, but I attempted installing the 17.1.1.273 update and it turned out I had already done that, also with patch 1.01dcp;1.02dcp;1.36;1.38;1.03dcp. Is this what you're referring to?

JohnT_Intel
Employee
306 Views

Hi,

 

Yes, may I know why you performed the update? Could you check how many Quartus is installed on your system?

RBash
Novice
306 Views

Hi,

 

Honestly, I don't remember why but yesterday I downloaded the update and wanted to install it, and encountered a message that said I have already installed the update and the patch. I have two Quartus installations, 18.0 for running HLS and 17.1.1 for synthesis, but before running synthesis I source the init_env.sh script in the Quartus 17.1.1 path which sets the QUARTUS_HOME environment variable to point to Quartus 17.1.1.

JohnT_Intel
Employee
306 Views

Hi,

 

Could you provide your system variable before you compile your design? I would like to make sure that the environment is correct.

RBash
Novice
306 Views

The following is the output of printenv. I removed other environment variables that are not related to Intel FPGA, if you're looking for a specific variable please let me know.

 

QSYS_ROOTDIR=/winhomes/rb274/intelFPGA_pro/18.0/qsys/bin INTELFPGAOCLSDKROOT=/opt/fpga/inteldevstack/intelFPGA_pro/hld QUARTUS_HOME=/opt/fpga/inteldevstack/intelFPGA_pro/quartus OPAE_PLATFORM_ROOT=/opt/fpga/inteldevstack/a10_gx_pac_ias_1_2_pv FPGA_BBB_CCI_SRC=/winhomes/rb274/intel-fpga-bbb-master AOCL_BOARD_PACKAGE_ROOT=/opt/fpga/inteldevstack/a10_gx_pac_ias_1_2_pv/opencl/opencl_bsp

 

JohnT_Intel
Employee
306 Views

Hi,

 

Could you change your environment for "QSYS_ROOTDIR" to /opt/fpga/inteldevstack/intelFPGA_pro/qsys/bin directory if not mistaken?

RBash
Novice
306 Views

Hi,

 

I changed it and tried again, but the same error happened again.

JohnT_Intel
Employee
306 Views

Hi,

 

I am not able to duplicate the issue from my side. May I know if you are able to try to compile in DevCloud https://software.intel.com/en-us/devcloud/FPGA. You can register it for free.

RBash
Novice
306 Views

Hi,

 

Thank you for your help, I'll give that a try.

JohnT_Intel
Employee
306 Views

Sure. I will wait for your update on your result.

RBash
Novice
306 Views

Sorry for my late response, I forgot to post the result here. I could successfully synthesize on DevCloud.

JohnT_Intel
Employee
306 Views

Glad that you are able to compile your design.

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