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System Verilog 2009 Generate Loop

Altera_Forum
Honored Contributor II
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How can I get this piece of code to compile? 

This works fine in other synthesis tools, simulation etc. Just trying to map it to an FPGA. 

 

In Quartus 17.1 and 18.0 I get this error: 

 

Error(13411): Verilog HDL syntax error at blah.sv(329) near text generate Error(13224): Verilog HDL or VHDL error at blah.sv(329): SystemVerilog 2009 keyword generate used in incorrect context  

 

 

 

generate for (genvar i=0; i<N; i++) for (genvar j=0; j<10; j++) assign status = status_ff]; endgenerate  

 

Any help will be appreciated. Thanks!!
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Altera_Forum
Honored Contributor II
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I don't think I've seen the genvar commands inside the loop before. Try putting genvar i and genvar j above the generate keyword. You might also want to try inserting begin/end around the inner for loop. And how and where is N defined? 

 

Also, why are you using generate for simple assignments? Can't you just use a normal for loop?
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Altera_Forum
Honored Contributor II
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Usually when you get an unexplainable syntax error, there is a problem with the code just before it.  

 

SystemVerilog added the ability to put the genvar inside the for loop. Verilog-2005 made the generate/endgenerate keywords optional. The compiler should be able to tell from the context whether the for-loop is a generate-for or a procedural-for. I would try removing them and seeing if you get a different error message.
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