System Verilog simulation control tasks in Questa not working

[lvcfdd]

Hello,

I am using the Questa Intel FPGA Edition-64 2023.3 version to run my simulations. My testbench is in System Verilog and when I try to use simulation control commands such as $stop, $monitor etc, Questa throws an error. The error message is pasted below.

(vlog-13161) unexpected '$stop', expecting elaboration system task $fatal/$error/$warning/$info

Is this a limitation of Intel Questa version or am I missing something? Has anyone come across this issue?

[ShengN_Intel]

Hi,

I try with a simple system verilog testbench which involved $stop, $monitor on Questa without any problem check attached.

Possible to provide your testbench for taking a look?

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Any further update or concern on this thread?

Thanks,

Best Regards,

Sheng