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BLee15
New Contributor I
636 Views

SystemVerilog attribute with multi-line string has weird behavior

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition

When I tried to synthesis following Verilog code:

(* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; \ -name VIRTUAL_PIN ON -to b[*]; \ -name VIRTUAL_PIN ON -to c[*]" *) module top( input logic raw_clock,   input logic[17:0] a, input logic[17:0] b, output logic[35:0] c ); logic clock; pll pll( .inclk0(raw_clock), .c0(clock) ); always_ff @(posedge clock) begin c <= a * b; end endmodule

I got following errors:

Warning (10306): Invalid value "744'b001011010110111001100001011011010110010100100000010101100100100101010010010101000101010101000001010011000101111101010000010010010100111000100000010011110100111000100000001011010111010001101111001000000110000101011011001010100101110100111011001000000000101000101101011011100110000101101101011001010010000001010110010010010101001001010100010101010100000101001100010111110101000001001001010011100010000001001111010011100010000000101101011101000110111100100000011000100101101100101010010111010011101100100000000010100010110101101110011000010110110101100101001000000101011001001001010100100101010001010101010000010100110001011111010100000100100101001110001000000100111101001110001000000010110101110100011011110010000001100011010110110010101001011101" for synthesis attribute "altera_attribute" at top.sv(1) Error (271004): Can't process assignment. Attribute format is illegal -- parsing error ' (line 5). Use legal format for ALTERA_ATTRIBUTE assignment. Error (271012): Can't process ALTERA_ATTRIBUTE "744'b001011010110111001100001011011010110010100100000010101100100100101010010010101000101010101000001010011000101111101010000010010010100111000100000010011110100111000100000001011010111010001101111001000000110000101011011001010100101110100111011001000000000101000101101011011100110000101101101011001010010000001010110010010010101001001010100010101010100000101001100010111110101000001001001010011100010000001001111010011100010000000101101011101000110111100100000011000100101101100101010010111010011101100100000000010100010110101101110011000010110110101100101001000000101011001001001010100100101010001010101010000010100110001011111010100000100100101001110001000000100111101001110001000000010110101110100011011110010000001100011010110110010101001011101" from design file

It seems that the string is converted to (very long-sized) binary number, which is not expected by altera_attribute.

If i remove backslash-newline instances (i.e. write string as one-line), the synthesis produced expected outcome without any errors.

 

If this is bug, could you guide formal issue report channels for student-level users?

If this is not bug, could you guide what was wrong?

0 Kudos
17 Replies
sstrell
Honored Contributor II
259 Views

I wouldn't think this is a bug. Backslash is a line extension for Tcl, not Verilog. You can add backslashes if you were to add these assignments to your .qsf file since that file is Tcl based. A .sv file is not.

 

#iwork4intel

BLee15
New Contributor I
259 Views

SystemVerilog 2005 (IEEE Std 1800-2005) Section 3.6 String literals says this:

 

A string literal must be contained in a single line unless the new line is immediately preceded by a \ (back slash). In this case, the back slash and the new line are ignored.

 

It seems that .sv should support backslash+newline inside string......

sstrell
Honored Contributor II
259 Views

Well, I guess I learned something today!

 

Perhaps it works in other parts of SV code but not in the middle of attributes. Have you tried that?

 

It might also be good to go into the Settings (from the Assignments menu) and under Verilog, make sure the SystemVerilog interpreter is set. Perhaps it's trying to synthesize your code as Verilog-2001 instead of SystemVerilog.

 

#iwork4intel

BLee15
New Contributor I
259 Views

When I tried backslash-newline in module parameter like this:

(* altera_attribute = "-name VIRTUAL_PIN ON -to a[*]; -name VIRTUAL_PIN ON -to b[*]; -name VIRTUAL_PIN ON -to c[*]" *) module top( input logic raw_clock, input logic[17:0] a, input logic[17:0] b, output logic[35:0] c ); logic clock; pll pll( .inclk0(raw_clock), .c0(clock) ); lpm_mult #( .lpm_widtha(18), .lpm_widthb(18), .lpm_widthp(36), .lpm_pipeline(1), .lpm_representation("UNS\ IGNED") ) mult( .clock(clock), .dataa(a), .datab(b), .result(c) ); endmodule

 

I got following error message:

Warning (272007): MGL_INTERNAL_WARNING: ( The parameter value is not one of the pre-specified values in the value list.) lpm_mult|LPM_REPRESENTATION The value assigned is UNS IGNED and the valid value list is UNSIGNED|SIGNED Error (272006): Parameter error: LPM_REPRESENTATION parameter with value UNS IGNED must be set to SIGNED or UNSIGNED

Whie it retains string type (i.e. not convertered to bitstream), it seems that the newline character is not ignored.

 

 

 

The following SystemVerilog source code, which includes type casting for attribute, caused crash (core dump) of quartus_map:

(* altera_attribute = string'("-name VIRTUAL_PIN ON -to a[*]; \ -name VIRTUAL_PIN ON -to b[*]; \ -name VIRTUAL_PIN ON -to c[*]") *) module top( input logic raw_clock, input logic[17:0] a, input logic[17:0] b, output logic[35:0] c ); logic clock; pll pll( .inclk0(raw_clock), .c0(clock) ); lpm_mult #( .lpm_widtha(18), .lpm_widthb(18), .lpm_widthp(36), .lpm_pipeline(1), .lpm_representation("UNSIGNED") ) mult( .clock(clock), .dataa(a), .datab(b), .result(c) ); endmodule

 

BLee15
New Contributor I
259 Views

The following source code, which uses concatenation operator for attribute, synthesised as expected without any errors.

 

(* altera_attribute = { "-name VIRTUAL_PIN ON -to a[*]; ", "-name VIRTUAL_PIN ON -to b[*]; ", "-name VIRTUAL_PIN ON -to c[*]" } *) module top( input logic raw_clock, input logic[17:0] a, input logic[17:0] b, output logic[35:0] c ); logic clock; pll pll( .inclk0(raw_clock), .c0(clock) ); lpm_mult #( .lpm_widtha(18), .lpm_widthb(18), .lpm_widthp(36), .lpm_pipeline(1), .lpm_representation("UNSIGNED") ) mult( .clock(clock), .dataa(a), .datab(b), .result(c) ); endmodule

 

 

As it seems that string concatenation is better option than backslash-newline idiom, I'll use this method. However, could you consider investigating this issue, especially the crashed case?

sstrell
Honored Contributor II
259 Views

As you show in your last example, you can just use whitespace (carriage return between words). There's no need to even use the backslash.

 

But did you check which language interpreter was being used as I mentioned?

 

#iwork4intel

BLee15
New Contributor I
259 Views

I'm pretty sure the language is SystemVerilog indeed.

 

  • The file extension is ".sv" (instead of ".v")
  • If it were Verilog mode, the keyword like 'logic' and/or 'always_ff' would be produce error.
MEIYAN_L_Intel
Employee
259 Views

Hi,

I had found out that information as below:

"To use the altera_attribute synthesis attribute in a Verilog Design File (.v) Definition or SystemVerilog Design File (.sv) Definition, add the attribute as a prefix to an object declaration using the Verilog 2001 attribute syntax (*...*). In addition, the synthesis attribute value must be a single string argument containing a list of QSF assignments separated by semicolons (;)"

Thanks

 

MEIYAN_L_Intel
Employee
259 Views

Hi,

May I know any update for this case?

Thanks

BLee15
New Contributor I
259 Views

I'm happy with Verilog concatenation operator, which I can handle arbitary long attributes as managable size.

 

Still, it seems that the crash during compile needs to be fixed.

MEIYAN_L_Intel
Employee
259 Views

Hi,

According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pd..., the Intel Quartus Prime Lite Edition software has limited language support for systemverilog. I had tried to compile the code in the Intel Quartus Prime Pro Edition software, there is no error occurred.

Thanks

BLee15
New Contributor I
259 Views

It seems that you are saying "You should bear with random compiler crashes because you didn't buy it." My opinion is that If some feature is unsupported in free version, it should present (nice) error message, instead of random crash.

MEIYAN_L_Intel
Employee
259 Views

Hi,

It is mentioned that random crashing behavior is observed in your previous reply, do you see a consistent error message for the error? I can see the same error message is issued by the software due to limited systemverilog language support in the Lite Edition of the software.

Thanks

BLee15
New Contributor I
259 Views

I mentioned that this source code caused crash (core dump) of quartus_map (which is different from very first source code):

 

(* altera_attribute = string'("-name VIRTUAL_PIN ON -to a[*]; \ -name VIRTUAL_PIN ON -to b[*]; \ -name VIRTUAL_PIN ON -to c[*]") *) module top( input logic raw_clock, input logic[17:0] a, input logic[17:0] b, output logic[35:0] c ); logic clock; pll pll( .inclk0(raw_clock), .c0(clock) ); lpm_mult #( .lpm_widtha(18), .lpm_widthb(18), .lpm_widthp(36), .lpm_pipeline(1), .lpm_representation("UNSIGNED") ) mult( .clock(clock), .dataa(a), .datab(b), .result(c) ); endmodule

 

 

Disclaimer: I can accept that the very first source code of this thread is due to limit support of lite edition.

MEIYAN_L_Intel
Employee
259 Views

Hi,

I can duplicate the crash as you mentioned and I had report this issue to the team.

The workaround is used concatenation operator for attribute.

Thanks

BLee15
New Contributor I
259 Views

Thanks for handling the issue.

I apologize using harsh language; I thought the crash report was completely ignored.

MEIYAN_L_Intel
Employee
259 Views

You are welcome.

Thanks

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