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SystemVerilog structure or struct assignment by keyword.

Branden_Allen
Beginner
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Description

I would like to assign values to a packed structure using keywords (e.g. code snippet below) but have run into the an apparent syntax error (10170) under Quartus 18.0.

 

I presume this means that this functionality is not yet supported but would like to confirm before I go through the trouble of altering my code.

 

Example

typdef struct packed { logic [15:0] data_type; logic some_flag; } hdr_t; hdr_t hdr= { data_type : '1, some_flag : 0 };

Error Message:

Error (10170): Verilog HDL syntax error at [FILENAME] near text: ":"; expecting "}".

 

Software Verison

Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition

 

 

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Branden_Allen
Beginner
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My Mistake:

 

I had a bit of code that omitted the "'" preceeding the assignment. The corrected code is included below:

 

typdef struct packed { logic [15:0] data_type; logic some_flag; } hdr_t; hdr_t hdr= '{ data_type : '1, some_flag : 0 };

 

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