TTK fails to run on Arria 10

[JPrig]

Hi,

I try to get TTK up and running on a custom Arria 10 design. My FPGA project is very simple.  I have a PLL which generates a system clock of 120MHz and a reset synchronized to this clock. I use the system clock to feed reconfig_clk of a single TX PHY (native PHY). I use the reset for reconfig_reset. I have also a transceiver PLL and a transceiver reset controller which is an IP from Intel. I connect them in a manner similar to a reference design I found: A10_native_rtl_ttk_q151. I have enabled all the options required for TTK, as specified in Arria 10 Transceiver User Guide.

The design compiles and programs, the sof file is auto-linked in TTK, but then I get this error:

Jul 13, 2021 10:19:21 AM com.altera.debug.core
SEVERE: TTK failed reading from PHY slave_2000, cannot enable TTK functionality for this PHY. Please verify the reconfig_clk is running and ensure this PHY is not stuck in reset.

I ran a SignalTap which sampled all PLL locked and resets with the system clock. All "locked" signals are high, the signal tap acquires data and all resets are low. Please advice how to proceed debugging this problem. I use Quartus 18.1.

[Deshi_Intel]

HI,

From the error message, it's basically complain about either your didn't provide reconfig_clk from your board or the transceiver is not release from reset properly.

• Can you double check your reconfig_clk (100MHz to 125MHz) and verify your transceiver power up sequence to ensure calibration is done and both PCS Tx_ready and Rx_ready signal are asserted ?
• Pls share with me your signal_tap file where you captured all the transceiver status signals from Transceiver PHY reset controller IP
• Another thing to watch out is did you provide clock frequency to FPGA clkusr pin as transceiver power up calibration clock ?
• other suggestion is pls reduce/disable your JTAG connection chain on board and also reduce the JTAG clock frequency from 24MHz to maybe 16MHz or 6MHz to see if it helps

Thanks.

Regards,

dlim

[Deshi_Intel]

Hi,

Thanks for sharing Quartus design.

1. NativePHY IP setting is fine.
2. I can see reconfig_clk and reconfig_reset connection is controlled by your own design "clock_reset_gen.vhd" but I don't see the signal_tap result. Pls share the signal_tap result file with me.
3. Other than that, you can look into some of my debug suggestion in my previous post.

Thanks.

Regards,

dlim

[JPrig]

Hi,

thanks for your suggestions. I have discovered that the reconfig_clk and reconfig_reset of the transceiver PLL were not connected. After I have connected them to system clock and reset, the error message disappeared and I am able to detect channels.

Thanks for the help.

Regards, Julia

[Deshi_Intel]

okok, I am glad issue is resolved at your end.

Alright, I am closing this case.

Thanks.

Regards,

dlim