I am using the Terasic DE5A-Net-DDR4 board PCIe_DDR4 reference desgin. The refrence design repository is of old Quartus verison. I am curently having Quartus 22.1 and I tried recompiling the design with this Quartus version by IP upgrade. It has compiled but ended up with timing vialations. I did not touched any of the settings. Can any body help me reason for the timing vilations with just re-compilation in the new Quartus verions ?
Thanks in Advance
Thank you for submitting your question in Intel Community.
May I know where I can get the design? I would like to replicate this issue at my end.
Which Quartus Edition that you are using? Is it a Pro Edition or Standard Edition?
Which Quartus version that you used to compile the design before?