I face one problem, when I use EMIF debug toolkit to test DDR4 board which is build by myself, and I get one example design under customize the requirement of the DDR4 which I need when I generate the EMIF IP. I compiled this example, and downloading .sof file into fpga. I open the EMIF debug toolkit and can create Memory Interface Connection, I can make sure that the calibration is completed and successful and can re-calibrate the IP through downloading the intruction through the EMIF DEBUG TOOLKIT to the IP. But when I creat Traffic Generator Connection, there is always one error that blocks me to do next operation.
About the information: I enable " Add EMIF Debug Interface" and select " Use configurable Avalon traffic generator 2.0" & Export Traffic Generator 2.0 configuration interface.
The error picture :
So about my problem, could one give me some advice?
The Traffic Generator 2.0 (TG2) is not supported in that old version of Quartus. You need to use at least 20.1 Pro.
Why it was an option in older versions of the tools is a mystery.
This training goes into detail on TG2. The training refers to Agilex, but I think it's supported in Arria 10 as well:
Though I can not create the Traffic Generator connection through EMIF Debug toolkit, that means I can not use many feature of the TG2.0 tool, I want to know if the traffic_gen_pass is asserted after TG2.0 IP in example project runover the some pattern (default traffic pattern, repeated-writes/repeated-reads test pattern, and stress pattern) under one datarate, can I think that the EMIF IP works well at the current frequency?
Whenever you reset the TG (TG or TG2), it goes through its pattern. But as mentioned, you're going to have to change your options to use the original TG and recompile your project to make this work unless you move to 20.1 or later (but even then you'd have to regenerate and recompile).