Hello there, i have problem. My tb file didnt work. Can someone please help me and test it?
I have Quartus 13.0 SP1. For simulation i use AlteraSim. Thanks a lot: VHDL file:library IEEE; --kniznica IEEEuse IEEE.STD_LOGIC_1164.ALL; --pouzitie IEEE.STD_LOGIC pre vyuzitie STD_LOGIC FUNKCII
entity rs_nand is -- popis entity
Port (rnot,snot: in STD_LOGIC; -- definovany port s log.vstupmi R, S
q,qb : out STD_LOGIC); -- VYSTUPY Q QB
end rs_nand; --koniec popisu entity
architecture rs_nand_arch of rs_nand is --popis architektury
signal tmp_q, tmp_qb : STD_LOGIC; -- vytvorenie logickych signalov tmp_q a tmp_qb
signal r,s : STD_LOGIC;
begin
r <= not rnot;
s <= not snot;
tmp_q <= snot NAND tmp_qb; -- popis signalu architektury na NAND hradle
tmp_qb <= rnot NAND tmp_q; -- popis signalu architektury na NAND hradle
q <= tmp_q; -- priradenie signalu tmp_q pre vystup q
qb <= tmp_qb; -- priradenie signalu tmp_qb pre vystup qb
end rs_nand_arch; --koniec popisu architektury
TB file: library IEEE; --kniznicause IEEE.STD_LOGIC_1164.ALL; --pouzitie log. funkcii STD_LOGIC
entity rs_nand is --opis entity
port(rnot, snot : in std_logic;
q, qb : out std_logic);
end rs_nand;
architecture rs_nand_arch of rs_nand is
signal tmp_q, tmp_qb : STD_LOGIC;
signal r, s : STD_LOGIC;
begin
tmp_q <= snot NAND tmp_qb;
tmp_qb <= rnot NAND tmp_q;
r <= not rnot;
s <= not snot;
q <= tmp_q;
qb <= tmp_qb;
end rs_nand_arch;
--------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rs_nand_tb is --entita testbench
end rs_nand_tb ;
architecture tb of rs_nand_tb is --architektura
component rs_nand is -- komponent rs_nand je komponentom architektury tb, ktora je pod entitou rs_nand_tb
port(rnot, snot : in std_logic; --port komponentu s vstupmi
q, qb : out std_logic); --vystupmi
end component; --uknceny popis komponentu
-------------
signal rnot, snot, q, qb : std_logic; --logicke signaly, ktore je mozne dalej opisat v port mappingu
-------------
begin
mapping: rs_nand port map(rnot, snot, q, qb); --mapovanie portov pre danu entitu
process --opis procesu. V procese je kod rovnocenny
--s <= '0'; a r <= '0';
-- je to isté ako r <= '0'; a s <= '0';
--rychlost vykonavania krokov v procese je identicka, nezalezi na poradi, riadku v kode
begin --zaciatok opisu procesov (ktore mozu nastat, stavy)
-------------TEST 1
snot <= '0';
rnot <= '0';
wait for 10 ns;
assert(q = '1') report "Error 1" severity error; --zakazany stav
assert(qb = '1'); --funkcia assert vie nastavit stav výstupu, moze aj referovat chybu!
----------TEST 2
snot <= '0';
rnot <= '1';
wait for 10 ns;
assert(q = '1'); --
assert(qb = '0');
----------TEST 3
snot <= '1';
rnot <= '0';
wait for 10 ns; --10ns caka v tomto stave
assert(q = '0');
assert(qb = '1');
----------TEST 4
snot <= '1';
rnot <= '1';
wait for 10 ns;
assert(q = q);
assert(qb = not q);
end process; --koniec opisu procesov
end tb; --koniec opisu architektury tb
configuration cfg_tb of rs_nand_tb is --konfiguracia test bench entity
for tb --cyklus je prazdny, nema ziadnu specificku funkciu v nasom pripade
end for; --koniec cyklu
end cfg_tb --koniec opisu konfiguracie
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You don't say what the problem is.
AlteraSim is clear.. Nothing show. Didnt see my project in left list too. Waveform simulation working OK, altera's not.
Do you mean Modelsim? Quartus has an internal simulator which only simulates compiled designs. Modelsim is a 3rd party simulator, where intel provides a copy for free.
So what simulator are you having problems with, and what exactly is the problem?Yes ModelSim-Altera. That's it. There is blank black window, where normally you can see waves. On left list, there isnt my design. Few days ago with older version of sketches it worked. I added r and s variables to that design. Only as signals std_logic. Because i simulate Rnot Snot flip flop. For that i must added (non negated) R and S. Can you please help me? Can you try that on your machine? I posted tb and normal vhd entity file.
Are there any errors in the transcript window?
Oh my god yes... ; missing at the end of last row. in tb. Error notice was "under" display. Thanks! Working.
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