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Altera_Forum
Honored Contributor I
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Testbench for 10G Ethernet PHY

Hello, 

I just implemented a 10G Ethernet PHY design using the IP core: "1G/2.5G/5G/10G Multi-rate Ethernet PHY" + pll & reset controller. 

The Ethernet PHY core should receive the serial data from an SFP+ modul (Stratix 10 SX FPGA) 

Now, I need to simulate the design to check if everything is working fine. 

I don't know which input data vector for the Ethernet PHY core I should use and which outputs should expect. 

 

Thanks a lot
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Altera_Forum
Honored Contributor I
31 Views

I suggest you refer to this Stratix 10 Low Latency Ethernet 10G MAC Design Example User Guide 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug-20073.pdf 

 

Chapter 6: 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices 

It provides an example to run the simulation. 

 

Regards, 

skbeh 

(This message was posted on behalf of Intel Corporation)
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