Hi everybody,I'm developing a project using Cyclone V FPGA in Quartus 15.1 Prime Lite edition (http://dl.altera.com/15.1/?edition=lite&lang=en). I have encountered with "strange" circumstances that some time when I synthesis my design (without changing it) I have a different sof output file. Therefore the main problem in this case is: when I program and execute the design on the development kit, the actual result of each design is different. I can not find out the root cause of this case. Please support me some advise and recommendation for this problem. Thank you!