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16009 Discussions

TimeQuest / DE1-SoC Design Contraint File

Honored Contributor II



I don't know what happened, but my topic got lost somehow - so here s another attampt. 






I've downloaded the SDC file for the DE1-SoC board from altera's university program page (


Beside other stuff, this file contains a clock generation for the SDRAM: 


create_clock -period "100 MHz" -name clk_dram  


My current design has to communicate with the SDRAM. Therefor, I use the "SDRAM controller" IP from Qsys and the "System and SDRAM clocks for DE-series boards" IP from the university program library. 

Using the latter IP I generate a system clock of 143MHz as well as s SDRAM clock with 143MHz and -153° phase shift (default value). The system clock is connected to the SDRAM Controller and the SDRAM clock 

to the corresponding output (DRAM_CLK). 

Because of that, I've replaced the line shown above by 

create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~FRACTIONAL_PLL|refclkin} -divide_by 10 -multiply_by 143 -duty_cycle 50.00 -name SDRAM_PLL_FRACTIONAL {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~FRACTIONAL_PLL|vcoph} create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 5 -duty_cycle 50.00 -name clk_dram_sys {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk} create_generated_clock -source {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|vco0ph} -divide_by 5 -phase -153.00 -duty_cycle 50.00 -name clk_dram {inst6|sys_sdram_pll_0|sys_pll|altera_pll_i|general.gpll~PLL_OUTPUT_COUNTER|divclk}  

The downloaded SDC file also contains some output delay constraints for inputs and outputs like (also for the VGA port, but I don't get warnings there):  

set_output_delay -max -clock clk_dram 1.452 set_output_delay -min -clock clk_dram -0.857 set_output_delay -max -clock clk_dram 1.531 set_output_delay -min -clock clk_dram -0.805  


When synthesizing the design, I get some "timing requirements not met" warnings created by TimeQuest and I'm not sure how to interpret them. This leads me to ask some questions: 

1) I've named the phase shifted clock clk_dram to match the output delay constraints. Is this correct or should I use the other clock? (In fact, I tried both - and both led to warnings). 

2) Do I have to change the "set_output_delay" constrains because of the changed (and increased) clock frequency? If yes, where can I find the matching values? 

3) What can I do to get rid of these warnings? I assume that the listed paths are not in my responsibility. 



I hope you can help me out  


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Honored Contributor II

PS: Here is an image of the timing analyzer results: