Timing Analysis Report

[Altera_Forum]

I have done a static timing analysis using TimeQuest Timing Analyzer for 100 MHz clock frequency for my design. I have got the following reports: 

 

1. Info (332140): No Setup paths to report 
2. Info (332140): No Hold paths to report 
3. Info (332140): No Recovery paths to report 
4. Info (332140): No Removal paths to report 
5. Info (332146): Worst-case minimum pulse width slack is 3.889 

  Info (332119): Slack End Point TNS Clock   Info (332119): ========= ============= =====================  Info (332119): 3.889 0.000 clk       What does it means? Does my design meets the clock requirement of 100 MHz?

[Altera_Forum]

Do you have syncronous logic? This is fast model?

[Altera_Forum]

Yes a synchronous logic. This is slow model.

[Altera_Forum]

Did you create a sdc file and add clock and include it into your quartus compile? Example: 

 create_clock -name "clkin" -period "100MHz" [ get_ports clk ]  If you have set the sdc file, you should get some figures on your setup/hold. +slack means meet and -ve slack means fail timing. Also you should be able to check your Fmax as well.

[Altera_Forum]

Path = flip-flop to flip-flop path so your design seem to have a problem

[Altera_Forum]

--- Quote Start ---  Did you create a sdc file and add clock and include it into your quartus compile? Example:  create_clock -name "clkin" -period "100MHz" [ get_ports clk ]  If you have set the sdc file, you should get some figures on your setup/hold. +slack means meet and -ve slack means fail timing. Also you should be able to check your Fmax as well.  --- Quote End ---     Yes I have created a SDC file for 100MHz frequency. then I have got this results. I dint no why any setup and hold slack is not there at the result. Do you have any idea? Foradditional info I am using Quartus 13.0 web edition.

[Altera_Forum]

It is likely your design is simple input assigned to output through one set of registers so there is no internal path. still you may have external io paths if you declare set_input_delay etc.

[Altera_Forum]

At the Compilation report, can you look at the TimeQuest Timing Analyzer tab -> Clocks, do you see your clock for your design and the assigned frequency?

[Altera_Forum]

--- Quote Start ---  At the Compilation report, can you look at the TimeQuest Timing Analyzer tab -> Clocks, do you see your clock for your design and the assigned frequency?  --- Quote End ---    Yes at the Compilation report, the clcoks tab under TimeQuest Timing Analyzer tab it shows the frequency information as I set (100 MHz)

[Altera_Forum]

Sounds weird to me. Would you be kind enough to archive your project file to .qar? I will try to go over quickly just to ensure that everything is ok.