Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17102 Discussions

Timing Analysis of Source Synchronous Outputs

Altera_Forum
Honored Contributor II
1,571 Views

Great Doc! Thanks!

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
807 Views

Hi kwalt, 

 

Thanks for the great technical note. It is really useful to learn how to do timing analysis of source sysncronous outputs. 

 

By the way, I have two questions on Tcl commands used in Figure 12. 

 

(1) 

What does "-no_report" option in "create_timing_netlist" do? I could not find the option in the Quartus II v7.1 Tcl help (quartus_sh --qhelp). 

 

(2) 

In which Tcl package is "open_timing_report" defined? I could not find this command in the Quartus II v7.1 Tcl help. 

 

As the script in Figure. 12 did not cause error, I guess those are defined somewhere. 

 

Thanks is advance.
0 Kudos
Reply