Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16606 Discussions

Timing Designer Inter-Path-Competition in Nios sub-system

CWarr1
Beginner
‎01-04-2021 04:37 AM
543 Views

Timing designer is reporting 'Inter-Path-Competition' issues for my Arria-10 FPGA design. The path that is highlighted is between the Nios processor and its associated onchip memory. Since both modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?
Thanks!

0 Kudos

Link Copied

2 Replies
sstrell
Honored Contributor III
‎01-04-2021 02:32 PM
534 Views

Can you show the error?  Timing info from the Timing Analyzer?  Need more details here.

I'm not sure what the "Timing Designer" is.  Do you mean the Design Assistant and you're failing a rule or something?

0 Kudos
Copy link
CWarr1
Beginner
‎01-05-2021 08:19 AM
521 Views
In response to sstrell

Apologies - I meant Timing Analyzer, not Timing Designer!

I will close this request and re-post with a corrected title

In response to sstrell
0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.