Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing/Fitter results depend on build system, Design fails timing by very small margin

AFies
Beginner
340 Views
Hello, we currently experience strange timing closure problems with a design. On my local workstation it usually works, even with "balanced" settings. The same design, same settings, same assignments on our CI build system fails frequently. Even when I increase to the highest speed optimized settings it fails with a small TNS of about -0.03ns. The problem therefore seems to be related to Quartus, not the design itself. The Quartus documentation says the results should be deterministic regardless of the system provided the seed and max CPU cores setting is identical, which is the case here. This statement is obviously false here, since even a 100% identical project produces different results on both systems. The hardware differs - the workstation is a Ryzen based system, the CI uses Xeons. I already tried to set a slack margin of 1ns, without any improvement. So the questions are: 1. Why do we see different results despite the documentation states otherwise? 2. How can we achieve deterministic results in the build process? 3. How can we fix the fitter giving up at this really small margin, since it is obviously not a design related issue? Thanks!
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1 Solution
SyafieqS
Moderator
308 Views

Hi Genua,


1. Why do we see different results despite the documentation states otherwise?


- Different result normally because of different environment of the machine. To preserve the timing, back annotate and design partition post fit can resolve this.

Can look in link below for details

https://www.youtube.com/watch?v=XO0Qi_zIpPs


 2. How can we achieve deterministic results in the build process? 


Few ways, to preserve place and route would be the best which there is a feature so called back annotate and design partition post fit. 


3. How can we fix the fitter giving up at this really small margin, since it is obviously not a design related issue? Thanks!


Small margin typically running seed sweep would resolve the issue. Another way is to implement set max/min delay for setup and hold respectively.






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4 Replies
SyafieqS
Moderator
309 Views

Hi Genua,


1. Why do we see different results despite the documentation states otherwise?


- Different result normally because of different environment of the machine. To preserve the timing, back annotate and design partition post fit can resolve this.

Can look in link below for details

https://www.youtube.com/watch?v=XO0Qi_zIpPs


 2. How can we achieve deterministic results in the build process? 


Few ways, to preserve place and route would be the best which there is a feature so called back annotate and design partition post fit. 


3. How can we fix the fitter giving up at this really small margin, since it is obviously not a design related issue? Thanks!


Small margin typically running seed sweep would resolve the issue. Another way is to implement set max/min delay for setup and hold respectively.






SyafieqS
Moderator
284 Views

Genua,


May I know if there is any update?


AFies
Beginner
274 Views

Hello, thanks for the reply. I suppose it may eventually help, though I have not been able to test everything.

Nonetheless, the documentation of Quartus needs to be fixed. It clearly says:

2.3.2. Enabling Multi-Processor Compilation

For a given Fitter seed, and given Maximum processors allowed setting on a specific design, the fit is exactly the same and deterministic. This remains true, regardless of the target machine, and the number of available processors. Different Maximum processors allowed specifications produce different results of the same quality. The impact is similar to changing the Fitter seed setting.

SyafieqS
Moderator
204 Views

Andreas,


Thanks for your feedback. I will file for doc enhancement. Let me know if there is any other concern from your end.



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