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Valued Contributor III
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Timing Problem(Clock Edge)

Dear all, 

 

I'm new to VHDL and need all u guys out there, 

 

I'm currently designning a VHDL code for traffic light (two processes) coding style and i bump to this error regarding clock timing: 

 

Error (10818): Can't infer register for "state.s0" at traffic.vhd(44) because it does not hold its value outside the clock edge 

 

Error (10818): Can't infer register for "state.s1" at traffic.vhd(44) because it does not hold its value outside the clock edge 

 

and so on......
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Valued Contributor III
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and de code: 

 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_arith.all; 

use IEEE.std_logic_unsigned.all; 

entity traffic is 

port ( 

 

CLK : in std_logic; 

RST : in std_logic; 

car : in std_logic; 

pedestrian : in std_logic; 

Digit1_o : out unsigned (3 downto 0); 

Digit10_o : out unsigned (3 downto 0); 

lights : out std_logic_vector (6 downto 0) 

 

); 

 

end traffic; 

architecture traffic_arch of traffic is 

type state_type is (s0,s1,s2,s3,s4,s5,s6,s7); 

signal state : state_type; 

signal Digit1 : unsigned (3 downto 0); 

signal Digit10 : unsigned (3 downto 0); 

 

begin 

main: process(CLK,RST,car,pedestrian) 

begin 

if pedestrian = '1' then 

state <= s4; 

 

if RST = '1' then 

state <= s0; 

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

 

if CLK'event and CLK = '1' then 

 

case state is 

 

when s0 => 

 

if Digit1 < 9 then 

state <= s0; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 5 then 

state <= s0; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s1;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

 

 

when s1 => 

 

if (car = '1') then 

state <= s2; 

 

else  

if Digit1 < 9 then 

state <= s1; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 2 then 

state <= s1; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s2;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

end if; 

 

when s2 => 

 

if Digit1 < 9 then 

state <= s2; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 0 then 

state <= s2; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s3;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

 

when s3 => 

 

if Digit1 < 2 then 

state <= s3; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 0 then 

state <= s3; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s4;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

 

when s4 => 

 

if Digit1 < 9 then 

state <= s4; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 2 then 

state <= s4; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s5;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

 

when s5 => 

 

if (car = '1') then 

if Digit1 < 9 then 

state <= s5; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 2 then 

state <= s5; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s6;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

 

if (car = '0') then 

state <= s6; 

 

end if; 

end if; 

end if; 

end if; 

 

when s6 => 

 

if Digit1 < 9 then 

state <= s6; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 0 then 

state <= s6; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s7;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

when s7 => 

 

if Digit1 < 2 then 

state <= s7; 

Digit1 <= Digit1 + 1; 

if 

Digit10 < 0 then 

state <= s7; 

Digit1 <= (others=>'0'); 

Digit10 <= Digit10 + 1; 

 

else  

state <= s0;  

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

end if; 

end if; 

 

 

when others => 

 

state <= s0; 

end case; 

 

end if; 

end if; 

end if; 

end process main; 

Digit1_o <= Digit1; 

Digit10_o <= Digit10; 

 

sub: process(state) 

begin 

case state is 

when s0 => 

lights <= "1011011"; 

 

when s1 => 

lights <= "1011011"; 

 

when s2 => 

lights <= "1010111"; 

 

when s3 => 

lights <= "1001111"; 

 

when s4 => 

lights <= "1101101"; 

 

when s5 => 

lights <= "1101101"; 

 

when s6 => 

lights <= "1101110"; 

 

when s7 => 

lights <= "1001111"; 

 

when others => 

lights <= "1011011"; 

 

end case; 

end process sub; 

 

end traffic_arch;
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Valued Contributor III
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This does not look correct to me at a first glance, I don't know if it is the only problem since I haven't got the time at the moment to try it. 

 

if RST = '1' then state <= s0; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); if CLK'event and CLK = '1' then ..  

 

"if CLK'event and CLK = '1' then" will only happen when the reset is high and the state variable will always in that case be set to 0. Try changing it to:  

 

if RST = '1' then state <= s0; Digit1 <= (others=>'0'); Digit10 <= (others=>'0'); elsif CLK'event and CLK = '1' then ...  

 

I wouldn't personally have any code outside the reset statement in a process to make sure nothing funny happens.
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Valued Contributor III
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I agree with Bango. 

Also with reference to the following 

 

 

--- Quote Start ---  

 

main: process(CLK,RST,car,pedestrian) 

begin 

if pedestrian = '1' then 

state <= s4; 

 

if RST = '1' then 

state <= s0; 

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

 

if CLK'event and CLK = '1' then 

 

 

case state is 

 

--- Quote End ---  

 

You would be better removing ,car,pedestrian from the sensitivity list. This is not required for synchronous processes. 

 

Also move the if clause  

 

--- Quote Start ---  

 

if pedestrian = '1' then 

state <= s4; 

 

--- Quote End ---  

 

Into the clocked part. 

 

So you should have something like 

 

main: process(CLK,RST) 

begin 

 

if RST = '1' then 

state <= s0; 

Digit1 <= (others=>'0'); 

Digit10 <= (others=>'0'); 

 

elsif CLK'event and CLK = '1' then 

if pedestrian = '1' then 

state <= s4; 

 

case state is 

... 

 

 

i.e. a reset clause and a sync clause and nothing else. You will need to check that this meets the functionality you expect. 

Hope this helps
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Valued Contributor III
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thanks for all ur comments.. i will try it out.. and certainly.. appreciate de help from u guys..

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Valued Contributor III
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de only problem that i facing now is that.. when i simulate.. de counter is not working and output stay at s0.. i tryin to detect everything but still failed.. wat can I do?

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Valued Contributor III
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Hello, 

 

If you post your new code in a file it is easier to help you directly. Otherwise I would suggest you look in the simulation and try to find the root of your problem. First check the clock and reset you generate in your testbench. If it still does not work you will have to start from the top and work yourself down until you find the problem. I know it's easier said then done but you will learn a lot more from that then someone telling you what is wrong. 

 

Best Regards, 

Ola Bångdahl
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Valued Contributor III
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thanks for all ur comments. i hav finished modifying de traffic code and now it is really works.. sorry if i bother u all too much..  

 

another question.. de prob that i facing now is that i want to generated a 1 Hz clock using clock divider method from the original crystal frequency of 33.333 MHz.. The FPGA board that I'm using is Apex20k EFC200-484 from Altera 

 

 

de code is as below : 

 

begin 

cloc:process(clk) 

variable cnt : integer range 0 to 16500000; 

begin 

if(clk'event and clk='1') then 

if(cnt=16500000)then 

cnt:=0; 

clkout<='1'; 

else 

cnt := cnt+1; 

clkout<='0'; 

end if; 

end if; 

end process cloc; 

 

 

I had compiled the code above.. and when i simulate for 2 seconds .. it took me overnite to finish .. anyone hav better idea than this method? thanks
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