Timing Violations in JTAG Signals

[FabianL]

Hello,

I have a Arria10 FPGA design using Platform Desginer which includes a Avalon to JTAG Brdige.

I have added a jtag.sdc file to the project based on this guideline: JTAG Signals

and set all the "--customize here--" sections according to my design (see attached sdc file).

However the Timing Analyzer gives me several setup violations on JTAG signals:

-18.207	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_8	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.240	Slow 950mV 100C Model
-18.206	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_9	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.239	Slow 950mV 100C Model
-18.157	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_7	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.190	Slow 950mV 100C Model
-18.142	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_10	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.175	Slow 950mV 100C Model
-18.123	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_11	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.156	Slow 950mV 100C Model
-18.120	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_6	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.153	Slow 950mV 100C Model
-17.207	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_1	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.697	Slow 950mV 0C Model
-17.136	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_3	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.626	Slow 950mV 0C Model
-17.069	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_2	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.559	Slow 950mV 0C Model
-17.064	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_4	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.554	Slow 950mV 0C Model
-16.972	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.462	Slow 950mV 0C Model
-16.075	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom~jtag_reg__nff	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-0.450	4.240	Slow 950mV 0C Model

The listed registers look similar but not identical to the security reg listing in the jtag.sdc line 86-89 which are to be ignored.

So I'm not sure if  these errors are actual errors caused, e.g. by a too high JTAG clock rate, or if these registers are just missing a respective false path due to encrypted core.

The Timing Analyzer does list the falling paths as encrypted:

Please advise how to deal with these JTAG signal in timing analysis.

Thanks

Fabian

[KennyTan_Altera]

By the way, any reason that you want to use 24Mhz? What is the use case and application that you are using that need this frequencies for Jtag? This is just for my understanding.

[KennyTan_Altera · Accepted solution]

After internal testing and discussion, we’ve confirmed the following for Arria 10 devices:

• Only the on-board USB-Blaster II is capable of supporting up to 24 MHz.
• The off-board USB-Blaster II cannot reach 24 MHz due to certain limitations
• That said, if the TDO pin of the Arria 10 is driving the TDI of another device through a short trace, it can still support up to 24 MHz.

In the SDC files, you’ll notice a placeholder such as <<customer here>>. This needs to be updated based on the actual trace length measurements on your board. If you're targeting 24 MHz, the timing constraints will need to be tighter to meet the higher frequency requirements.

I'll attach a sample SDC file that helps close timing at higher speeds. Let me know if you have any further questions.

[KennyTan_Altera]

Please note that this is just an example, we are changing the value all the way to:

set tck_blaster_tco_min 14.603

set tck_cable_min 10.00

These values are defined by the timing characteristics of the USB-Blaster II (UBII) hardware and cannot be modified by the user unless an on-board UBII implementation is being used.

Even with an on-board setup, the tck_blaster_tco_min value is unlikely to change significantly, as the TCO (Time Clock to Output) of the MAX10 output pin is likely the dominant factor.

However, for the on-board solution, the tck_cable_min—which represents the delay introduced by the physical cable and header—can be reduced considerably, especially when replacing the typical UBII cable and header with a more optimized trace path.

[KennyTan_Altera]

Do let me know if you have further question? If no, we shall close this thread.

[KennyTan_Altera]

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

[FabianL]

Thanks with the explanation. So the default setting of the USB Blaster II (if using offboard Blaster) with 24 MHz is not possible with Aria10 devices.

I guess that is fine for our application. At least now we know about this restriction and can handle it.

Thanks

Fabian