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DNguy4
Beginner
3,192 Views

Timing analysis on EMIF block

Hi,

I am having a strange issue when doing timing analysis on my design. I am using the Intel external memory interface IP (emif) in my design and the timing analysis tool cannot recognize the user clock output of the emif block. Even the get_clocks command cannot find this user clock. Is there anything I need to do to the emif block to make the tool recognizing the user clock output? The tool can recognize all other clocks in my design except this one.

Thanks

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14 Replies
BoonT_Intel
Moderator
45 Views

timing_usr_clk.JPGHi,

Do you made some modification to the IP?

I created a design and used the emif user clock.

I can see the *core_usr_clk is recognize by default.

DNguy4
Beginner
45 Views

hi,

I did not make any change to the IP. I just regenerate it and use it in the project. I am using Quartus 18.1. You can see that there is no user clock in the list of clock for the get_clocks command. I name it emif_usr_clk and it is not in the list.

 

sstrell
Honored Contributor II
45 Views

Have you connected this clock up to your user logic yet? Not sure if you're using Platform Designer or not, but in the Block Symbol diagram or the instantiation template for the IP, do you see the clock output enabled?

DNguy4
Beginner
45 Views

sstrell,

I check out the IP, initiate it, regenerate the IP (during the first compilation) and use it from there. The design is actually working in hardware (on Intel development board). I just want to do timing analysis to make sure that timing is o.k. and i discover this issue.

sstrell
Honored Contributor II
45 Views

I asked because if it was not connected, it would not show up as a clock in the Name Finder, like you show in your screenshot. The signal has to drive a clock input to be recognized as a clock domain. Try using the get_pins filter just to make sure it's not connected incorrectly.

 

Can you run Report Clocks in the timing analyzer and see this clock there?

BoonT_Intel
Moderator
45 Views

Thanks sstrell.

To run report clock.

Goto 'reports' tab, point to 'diagnostic' and click 'report clocks'.

DNguy4
Beginner
45 Views

the attached screen shows that the emif user clock is not in the clock report. I also attache the RTL screen shot showing that user clock is connected to other device (see the red highlighted net). This case is very strange.

I can send you the design if you want.

(it looks like i can only attach one file at a time, so check the next two posts for other files)

DNguy4
Beginner
45 Views

RTL showing user clock is connected to other logic.

DNguy4
Beginner
45 Views

RTL showing user clock is connected to other logic.

BoonT_Intel
Moderator
45 Views

I will suggest you generate the example design and see if the example design have the same problem. If example design usr clk is being detected, then make comparison between your design with example design.

DNguy4
Beginner
45 Views

i found some conflicts in the sdc file that confuses the tool. it is fixed now.

Thank you for your help.

BoonT_Intel
Moderator
45 Views

Hi can you share the details of the conflict here? So that it can benefit other that facing the similar problem. Thanks in advance.​

DNguy4
Beginner
45 Views

BCT_Intel,

when i generate the IP, the tool knows the frequency of the reference clock. If I create the reference clock clock in the top level sdc again, it get confused, even with the -add option. I remove the reference from the top level sdc and the tool is happy.

BoonT_Intel
Moderator
45 Views

@DNguy4​ Thank you!​

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