Timing analyzer warning related to signaltap

[SDe_J]

Hello Intel forums

I have a project in Quartus prime pro 18.1 which has a signaltap instance. When I compile, I get these warnings during the timing analysis:

Warning(332182): No path is found satisfying assignment "set_max_skew -from [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_transeiver_test|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|jtag_acq_clk_xing|intel_stp_status_bits_cdc_u1|stp_status_bits_in_reg[*]}] -to [get_registers {auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|auto_signaltap_transeiver_test|sld_signaltap_inst|sld_signaltap_body|sld_signaltap_body|jtag_acq_clk_xing|intel_stp_status_bits_cdc_u1|stp_status_bits_out[*]}] 1.000 ". This assignment will be ignored.

This same warning is repeated six times. For reference, my signaltap instance is called Transceiver_Test.

It doesn't seem to affect the behavior of my project or signaltap, but I'd like to understand the warning.

I'm building a project for a stratix 10 H-tile dev kit (1SG280HU2F50E2VG)

[bitwise]

The ignored SDC was constraining skew across a group of signals, but the specific signals don't exist in your design.  The assignment is thus ignored, and since the specified signals don't exist the fact that they won't have constrained skew is innocuous.  If you open the Timequest GUI and run the diagnostic report to tell you what constraints were ignored then it should tell you if this ignored constraint was in your SDC file or embedded in HDL.

[Nathan_R_Intel]

Yes, the ignored SDC was potentially containing signals that did not exist in your design. One question: did you build a fresh copy of design using Quartus Prime Pro 18.1 or migrated from other Quartus Prime version?

Regards,

Nathan