Timing fails for reset line

[Altera_Forum]

Happy new year, everybody! 

 I have a rather large design here, and am trying to get the timing constraints straight. So far most of my I/O Constraints are ok. I'm still struggling with some Clock Crossing bridges, but most of all the reset line to the NIOS.  The design is a biiig SOPC system (EP3C40 maxed out on RAM Cells for Periphereal FIFOs).   I have a fast Core clock domain (aimed at 100MHz), and a slower Periphereal clock (aimed at 50MHz). The reset line fails timing (Setup and Recovery) for a large number of blocks, with connections from node "mySOPC_NIOS:inst|mySOPC_NIOS_reset_clk_core_domain_synch_module:mySOPC_NIOS_reset_clk_core_domain_synch|data_out".  nReset is, however, currently unused and tied to VCC, and only synchronized within the SOPC.  I have already reduced the core clock to 50MHz and the perih. clock to 12MHz, but that had no effect on the slack.  Is there a way to lighten timing requirements to this internal line?

[Altera_Forum]

You haven't indicated if your reset signals are pre-synchronised to each clock domain. 

If not, you need a two stage synchroniser for each domain reset. These two registers themselves be set as false paths. You may then apply the reset to the asynchronous ports of flips (and check recovery/removal) or apply it synchronously to flips(and check ordinary tSU/tH). notice also that clock speed has little effect on hold/removal violations which may occur at any speed unlike tSU/recovery violations which are the limiting factor for fmax

[Altera_Forum]

Huh? 

I don't understand. I have a VCC line, going into nReset of the SOPC.  How can I add reset synchronizers inside the SOPC? Isn't that autogenerated by the tools (I'm using the 9.1 toolchain) ?