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DeusMMJr
Novice
1,080 Views

Timing issues using Arria 10 Dev kit for massive design

Hi, i'm working with a huge design using Arria 10 Dev kit and i'm facing with timing issues after signoff analysis. These time issues are associated specially with DSP blocks where long combinational paths are reported. So, the first idea would be redesign long combinational paths, but, in case of this solution is bad for design performance, the second idea would be apply a good floorplan, just to help Quartus solve timing issues. And, I'm in second option, trying to do the best floorplaning as possible. What can you suggest to do more? The design still have time violations for DSP blocks....

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GuaBin_N_Intel
Employee
44 Views

Yes, you have to reduce the comb path if the logic level is too many. Have you registered the output of DSP block? It would help if you could pipeline those outputs to traverse much longer distance in the path( more LABs).

DeusMMJr
Novice
44 Views

Thank you GNg! Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br<http://www.fieb.org.br> (71) 3462-8404 deusdete.junior@fieb.org.br
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