Timing problems even though quartus says circuit meets timing requirements

[Altera_Forum]

I have a design that works correctly when clocked around 25 MHz (everything is clocked by a single PLL). Quartus's Classic Timing Analyzer gives an "actual time" of 63.24 MHz. If I bump the PLL up to 60 MHz, Quartus compiles without any timing warnings ("All timing requirements were met for slow timing model timing analysis."). Actually trying to run on the FPGA board at this speed, however, it isn't running correctly. 

 How can clock speed affect circuit behavior even though Quartus claims it's okay?

[Altera_Forum]

Have you got any logic generated clocks? 

How about ansyncronous set/resets? latches?  The timing analyser can only check register to register timing, It cant cope with any of the above. If you have any of the above, you have a poor design that will cause the problems you describe.

[Altera_Forum]

In adition to Tricky's recomendations, a few things more you may want to check. 

 There's usually more than one model per device. Were the timing requirements met for all of the timming models?   Does your input clock have jitter and have you added uncertanty to account for it?  Can the rest of the board cope with 60 MHz and have you properly specified the I/O constraints?